Efficient implementation of a planar clock routing with the treatment of obstacles

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 10, 2000, Pages 1220-1225

  Kim, Haksu ^a  

^a University of North Carolina at Charlotte   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; TREES (MATHEMATICS); VLSI CIRCUITS;

CUTTING LINE EMBEDDING ALGORITHM; PLANAR CLOCK ROUTING; ZERO SKEW CLOCK ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034292749     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.875342     Document Type: Article

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