A practical transistor-level dual threshold voltage assignment methodology

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 421-426

  Gupta, Puneet ^c   Kahng, Andrew B ^a,b,c   Sharma, Puneet ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Blaze DfM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP DESIGNERS; CRITICAL DESIGN; DUAL-THRESHOLD VOLTAGE ASSIGNMENT; LEAKAGE REDUCTION; PROPAGATION DELAYS; RUNTIME LEAKAGE; SOLUTION QUALITY; TRANSITION DELAYS;

DESIGN;

LEAKAGE CURRENTS;

EID: 34547219885     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.13     Document Type: Conference Paper

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