The O-sequence: Representation of 3D-floorplan dissected by rectangular walls

PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings

Volumn , Issue , 2006, Pages 317-320

  Ohta, Hidenori ^a   Yamada, Toshinori ^b   Kodama, Chikaaki ^a   Fujiyoshi, Kunihiro ^a  

^a TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^b SAITAMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

THREE DIMENSIONAL; TREES (MATHEMATICS);

3D-FLOORPLAN; RECTANGULAR WALLS; SLICING TREES;

VLSI CIRCUITS;

EID: 34547335953     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. H. Kohira, C. Kodama, K. Fujiyoshi, and A. Takahashi. 3-D floorplanning for scheduling of dynamically reconfigurable systems. Technical Report of IEICE, VLD2004-67:pages 37-42, 2004. (in Japanese).
3. Cheng Lei, Deng Liang, and D.F. Wong. Floorplan design for 3-D ICs. In Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2004), pages 395-401, 2004.
4. H. Ohta, T. Yamada, and K. Fujiyoshi. On the number of rooms in a rectangular solid dissection. In The 18th Workshop on Circuits and Systems in Karuizawa, pages 607-612, 2005.
5. K. Sakanushi and Y. Kajitani. The quarter-state sequence (Q-sequence) to represent the floorplan. IEEE Trans, on CAS-l, 50(3):376-386, 2003.
6. H. Yamazaki, K. Sakanushi, S. Nakatake, and Y. Kajitani. The 3D-packing by meta data structure and packing heuristics. IEICE Trans. Fundamentals, E83-A(4):639-645, 2000.
7. P. H. Yuh, C. L. Yang, Y. W. Chang, and H. L. Chen. Temporal floorplanning using 3D-subTCG. In Proc. Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004), pages 725-730, 2004.