Three dimensional module packing by simulated annealing

2005 IEEE Congress on Evolutionary Computation, IEEE CEC 2005. Proceedings

Volumn 2, Issue , 2005, Pages 1069-1074

  Yamagishi, Hirokazu ^a   Ninomiya, Hiroshi ^b   Asai, Hideki ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

^b SHONAN INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS; OPTIMIZATION; SIMULATED ANNEALING; VLSI CIRCUITS;

CHIP DESIGN; CODING SYSTEMS; NONOVERLAPPING CONSTRAINTS; OPTIMIZATION ALGORITHMS;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 27144447049     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. K.Banerjee, S.J.Souri, P.Kapur, and K.C.Saraswat, "3-D ICs: A novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," Proc. of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
2. T.Kawakami, M.Minagawa, and Y.Kakuzu, "Automatic Tuning of 3-D Packing Strategy and Rule-Base Construction Using GA," Trans. of IPSJ, vol. 30, no. 6, pp. 761-768, 1992.
3. H.Yamamoto, Y.Nakayama, H.Ninomiya, and H.Asai, "A Neuro-Based Optimization Algorithm for Rectangular Puzzles," IEICE Trans. Fundamentals, vol. E81-A, no. 6, pp. 1113-1118, 1998.
4. P.H.Yuh, C.L.Yang, Y.W.Chan and II.L.Chen, "Temporal Floorplanning Using 3D-subTCG," Proc. ASP-DAC'04, pp. 725-730, Jan 2004.
5. H.Kawai and K.Fujiyoshi, "3D-Block Packing using a Tree Representation," IEICE Technical Report, VLD2004-29, pp. 49-54, June 2004.
6. H.Yamazaki, K.Sakanushi, S.Nakatake, and Y.Kajitani, "The 3D-Packing by Meta Data Structure and Packing Heuristics," IEICE Trans. Fundamentals, vol. E83-A, no. 4, pp. 639-645, April 2000.
7. H.Murata, K.Fujiyoshi, S.Nakatake, and Y.Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. on CAD, vol. 15, no. 12, pp. 1518-1524, Dec 1996.
8. S.Nakatake, K.Fujiyoshi, H.Murata, and Y.Kajitani, "Module Packing Based on the BSG-Structure and IC Layout Applications," IEEE Trans. on CAD, vol. 17, no. 6, pp. 519-530, June 1998.