Redundant-digit floating-point addition scheme based on a stored rounding value

IEEE Transactions on Computers

Volumn 59, Issue 5, 2010, Pages 694-706

  Jaberipur, Ghassem ^a,b   Parhami, Behrooz ^c   Gorgin, Saeid ^a  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b INSTITUTE FOR RESEARCH IN FUNDAMENTAL SCIENCES IPM   (Iran)

^c University of California   (United States)

Author keywords

Adder subtractor; Computer arithmetic; Floating point; Redundant format; Rounding; Signed digit number system

Indexed keywords

ADDITION ALGORITHMS; APPLICATION-SPECIFIC SYSTEMS; CIRCUIT DESIGNS; CIRCUIT TECHNIQUES; COMPUTER ARITHMETIC; DIGIT REPRESENTATION; EMBEDDED ENCODING; FLOATING POINT NUMBERS; FLOATING POINTS; FLOATING-POINT ADDER; FLOATING-POINT ADDITION; HARDWARE REDUNDANCY; IEEE-754; INHERENT COMPLEXITY; LATENCY REDUCTION; LOW-LATENCY; POWER DISSIPATION; POWER SAVINGS; REDUNDANT REPRESENTATION; SIGNED-DIGIT NUMBER SYSTEMS; SUBFUNCTIONS;

ADDERS; DESIGN; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT MANUFACTURE; PARALLEL PROCESSING SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 77950318688     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2009.152     Document Type: Article

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