The case for a redundant format in floating point arithmetic

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2003, Pages 95-102

  Fahmy, Hossam A H ^a   Flynn, Michael J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; TRANSISTORS;

REDUNDANT FORMATS;

DIGITAL ARITHMETIC;

EID: 0043136386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. IEEE standard for binary floating-point arithmetic, Aug. 1985. (ANSI/IEEE Std 754-1985).
2. J. D. Bruguera and T. Lang. Leading-one prediction with concurrent position correction. IEEE Transactions on Computers, 48(10): 1083-1097, Oct. 1999.
3. M. Daumas and D. Matula. Recoders for partial compression and rounding. Research Report No. RR97-01, Laboratoire de l'Informatique du Parallélisme, Ecole Normale Supérieure de Lyon, Jan. 1997. Available at http://www.enslyon.fr/LIP/Pub/rr1997.html.
4. M. Daumas and D. Matula. Further reducing the redundancy of a notation over a minimally redundant digit set. Research Report No. RR2000-09, Laboratoire de l'Informatique du Parallélisme, Ecole Normale Supérieure de Lyon, Mar. 2000. Available at http://www.enslyon.fr/LIP/Pub/rr2000.html.
5. H. A. H. Fahmy, A. A. Liddicoat, and M. J. Flynn. Improving the effectiveness of floating point arithmetic. In Thirty-Fifth Asilomar Conference on Signals, Systems, and Computers, Asilomar, California, USA, volume 1, pages 875-879, Nov. 2001.
6. H. A. H. Fahmy, A. A. Liddicoat, and M. J. Flynn. Parametric time delay modeling for floating point units. In The International Symposium on Optical Science and Technology, SPlE's 47th annual meeting (Arithmetic session), Seattle, Washington, USA, July 2002.
7. P. M. Farmwald. On the Design of High Performance Digital Arithmetic Units. PhD thesis, Stanford University, Aug. 1981.
8. A. A. Liddicoat. High-Performance Arithmetic for Division and The Elementary Functions. PhD thesis, Stanford University, Feb. 2002.
9. A. A. Liddicoat and M. J. Flynn. High-performance floating point divide. In Proceedings of the Euromicro Symposium on Digital System Design, pages 354-361, Sept. 2001.
10. D. W. Matula and A. M. Nielsen. Pipelined packet-forwarding floating point: I. foundations and a rounder. In Proceedings of the 13th IEEE Sympsoium on Computer Arithmetic, Asilomar, California, USA, pages 140-147, July 1997.
11. G. W. McFarland. CMOS Technology Scaling and Its Impact on Cache Delay. PhD thesis, Stanford University, June 1997.
12. A. M. Nielsen, D. W. Matula, C. N. Lyu, and G. Even. An IEEE compliant floating-point adder that conforms with the pipelined packet-forwarding paradigm. IEEE Transactions on Computers, 49(1):33-47, Jan. 2000.
13. B. Parhami. Generalized signed-digit number systems: A unifying framework for redundant number representations. IEEE Transactions on Computers, 39(1):89-98, Jan. 1990.
14. B. Parhami. On the implementation of arithmetic support functions for generalized signed-digit number systems. IEEE Transactions on Computers, 42(3):379-384, Mar. 1993.
15. D. S. Phatak and I. Koren. Hybrid signed-digit number systems: A unified framework for redundant number representations with bounded carry propagation chains. IEEE Transactions on Computers, 43(8):880-891, Aug. 1994.
16. N. Quach and M. J. Flynn. Leading one prediction - implementation, generalization, and application. Technical Report No. CSL-TR-91-463, Computer Systems Laboratory, Stanford University, Mar. 1991.
17. N. T. Quach. Reducing the latency of floating-point arithmetic operations. PhD thesis, Stanford University, Dec. 1993.