Further reducing the redundancy of a notation over a minimally redundant digit set

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 33, Issue 1-2, 2003, Pages 7-18

  Daumas, Marc ^a   Matula, David W ^b  

^a UNIVERSITÉ DE LYON   (France)

^b Southern Methodist University   (United States)

Author keywords

Addition; Computer arithmetic; Multiplication; Redundant notation

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION THEORY; MATHEMATICAL OPERATORS; REDUNDANCY; SET THEORY;

COMPUTER ARITHMETIC;

VLSI CIRCUITS;

EID: 0037285993     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1021133616373     Document Type: Article

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