Weighted two-valued digit-set encodings: Unifying efficient hardware representation schemes for redundant number systems

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 7, 2005, Pages 1348-1357

  Jaberipur, Ghassem ^a   Parhami, Behrooz ^b   Ghodsi, Mohammad ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b University of California   (United States)

Author keywords

Arithmetic unit; Carry free addition; Computer arithmetic; Digit set; Hybrid redundancy; Number representation; Redundant number system; Signed digit number system; Stored transfer representation; Weighted bit set (WBS) encoding

Indexed keywords

ADDERS; ENCODING (SYMBOLS); NUMBER THEORY; OPTIMIZATION; REDUNDANCY; SET THEORY;

ARITHMETIC UNIT; CARRY FREE ADDITION; COMPUTER ARITHMETIC; DIGIT SETS; HYBRID REDUNDANCY; NUMBER REPRESENTATION; REDUNDANT NUMBER SYSTEM; SIGNED DIGIT NUMBER SYSTEM; STORED TRANSFER REPRESENTATION; WEIGHTED BIT SET (WBS) ENCODING;

DIGITAL ARITHMETIC;

EID: 23144458549     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.851679     Document Type: Article

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