Rounding in redundant digit floating point systems

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5205, Issue , 2003, Pages 473-481

  Fahmy, Hossam A H ^a   Flynn, Michael J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Floating point units; Redundancy; Rounding; Signed digits

Indexed keywords

ADDERS; ALGORITHMS; CRITICAL PATH ANALYSIS; NUMBER THEORY; OPTIMIZATION; REDUNDANCY; TREES (MATHEMATICS);

ARITHMETIC UNITS; DIGIT FLOATING POINT SYSTEMS; ROUNDING; SIGNED DIGITS;

DIGITAL ARITHMETIC;

EID: 1842555460     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. P. M. Farmwald, On the Design of High Performance Digital Arithmetic Units. PhD thesis, Stanford University, Aug. 1981.
2. N. T. Quach, Reducing the latency of floating-point arithmetic operations. PhD thesis, Stanford University, Dec. 1993.
3. A. Beaumont-Smith, N. Burgess, S. Lefrere, and C. C. Lim, "Reduced latency IEEE floating-point standard adder architectures," in Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, pp. 35-42, Apr. 1999.
4. P.-M. Seidel and G. Even, "On the design of fast IEEE floating-point adders," in Proceedings of the 15th IEEE Symposium on Computer Arithmetic, Vail, Clorado, USA, pp. 184-194, July 2001.
5. H. A. H. Fahmy, A. A. Liddicoat, and M. J. Flynn, "Parametric time delay modeling for floating point units," in The International Symposium on Optical Science and Technology, SPIE's 47th annual meeting (Arithmetic session), Seattle, Washington, USA, July 2002.
6. M. R. Santoro, G. Bewick, and M. A. Horowitz, "Rounding algorithms for IEEE multipliers," in Proceedings of the 9th IEEE Symposium on Computer Arithmetic, Santa Monica, California, USA, pp. 176-183, Sept. 1989.
7. M. I. Furgeson and M. D. Ercegovac, "The IEEE rounding for multiplier with redundant operands," in Thirty-Fourth Asilomar Conference on Signals, Systems, and Computers, Asilomar, California, USA, 2, pp. 1334-1338, Oct. 2000.
8. H. A. H. Fahmy and M. J. Flyn, "The case for a redundant format in floating point arithmetic," in Proceedings of the 16th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003.
9. H. A. H. Fahmy, A Redundant Digit Floating Point System. PhD thesis, Stanford University, June 2003.