Constant-time addition with hybrid-redundant numbers: Theory and implementations

Integration, the VLSI Journal

Volumn 41, Issue 1, 2008, Pages 49-64

  Jaberipur, Ghassem ^a,b   Parhami, Behrooz ^c  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b INSTITUTE FOR STUDIES IN THEORETICAL PHYSICS AND MATHEMATICS IPM   (Iran)

^c Santa Barbara   (United States)

Author keywords

Arithmetic unit; Carry free addition; Computer arithmetic; redundant number representation; Signed digit number system

Indexed keywords

ADDERS; DIGITAL ARITHMETIC; ELECTRIC INVERTERS; PROBLEM SOLVING; REDUNDANCY; VLSI CIRCUITS;

ARITHMETIC UNIT; CARRY-FREE ADDITION; COMPUTER ARITHMETICS; REDUNDANT NUMBER REPRESENTATION; SIGNED-DIGIT NUMBER SYSTEM;

NUMBER THEORY;

EID: 34548502918     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.01.002     Document Type: Article

References (26)

1. Parhami B. Computer Arithmetic: Algorithms and Hardware Designs (2000), Oxford University Press, Oxford
2. Avizienis A. Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electronic Comput. 10 (1961) 389-400
3. Gonzalez A.F., and Mazumder P. Redundant arithmetic, algorithms, implementations. Integration VLSI J. 30 (2000) 13-53
4. Ercegovac M.D., and Lang T. Effective coding for fast redundant adders using the radix-2 digit set { 0, 1, 2, 3 }. Proceedings of the Asilomar Conference of Signals, Systems, and Computers (November 1997) 1163-1167
5. Jaberipur G., and Ghodsi M. High radix signed digit number systems: representation paradigms. Sci. Iran. 10 4 (2003) 383-391
6. Jaberipur G., Parhami B., and Ghodsi M. A class of stored-transfer representations for redundant number systems. Proceedings of the 35th Asilomar Conference Signals Systems and Computers (November 2001) 1304-1308
7. Phatak D.S., and Koren I. Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains. IEEE Trans. Comput. 43 8 (1994) 880-891
8. Parhami B. Generalized signed-digit number systems: a unifying framework for redundant number representations. IEEE Trans. Comput. 39 1 (1990) 89-98
9. Aoki T., Sawada Y., and Higuchi T. Signed-weight arithmetic and its application to a field-programmable digital filter architecture. IEICE Trans. Electronics E82-C 9 (1999) 1687-1698
10. Jaberipur G., Parhami B., and Ghodsi M. Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Trans. Circuits Syst. I 52 7 (2005) 1348-1357
11. G. Jaberipur, B. Parhami, Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic, IET Proceedings of the Circuits, Devices, and Systems, 2007, to appear.
12. Phatak D.S., and Koren I. Constant-time addition and simultaneous format conversion based on redundant binary representations. IEEE Trans. Comput. 50 11 (2001) 1267-1278
13. Kornerup P. Reviewing 4-to-2 adders for multi-operand addition. J. VLSI Signal Process. 40 (2005) 143-152
14. Lue J.J., and Phatak D.S. Area × delay (AT) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation. Proceedings of the 14th IEEE Symposium Computer Arithmetic (1999) 216-224
15. Kornerup P. Digit-set conversions: generalizations and applications. IEEE Trans. Comput. 43 5 (1994) 622-629
16. Jaberipur G., Parhami B., and Ghodsi M. An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding. J. VLSI Signal Process. 42 2 (2006) 149-158
17. Parhami B. On the implementation of arithmetic support functions for generalized signed-digit number systems. IEEE Trans. Comput. 42 3 (1993) 379-384
18. Kuninobu S., Nishiyama T., Edamatsu H., Taniguchi T., and Takagi N. Design of high speed MOS multiplier and divider using redundant binary representation. Proceedings of the 8th IEEE Sympoisum Computer Arithmetic (1987) 80-86
19. Bui H.T., Wang Y., and Jiang Y. Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Trans. Circuits Syst. II 49 1 (2002) 25-30
20. Chang C.H., Gu J., and Zhang M. A Review of 0.18-μ m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst. 13 6 (2005) 686-695
21. Sayed A., and Al-Asaad H. Survey and evaluation of low-power full-adder cells. Proceedings of the International Conference on VLSI (2004) 332-338
22. Daumas M., and Matula D.W. Further reducing the redundancy of a notation over a minimally redundant digit set. J. VLSI Signal Process. 33 (2003) 7-18
23. Pezaris S.D. A 40-ns 17-bit by 17-bit array multiplier. IEEE Trans. Comput. 20 (1971) 442-447
24. Wallace C.S. A suggestion for a fast multiplier. IEEE Trans. Electronic Comput. 13 (1964) 14-17
25. Dadda L. Some schemes for parallel multipliers. Alta Freq. 34 (1965) 349-356
26. Kornerup P. Necessary and sufficient conditions for parallel, constant time conversion and addition. Proceedings of the 14th IEEE Symposium Computer Arithmetic (1999) 152-155