A 1ps-resolution jitter-measurement macro using interpolated jitter oversampling

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Nose, Koichi ^a   Kajita, Mikihiro ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIERARCHICAL SYSTEMS; INTERPOLATION; OPTICAL RESOLVING POWER; REAL TIME SYSTEMS;

FEEDFORWARD CALIBRATION; JITTER OVERSAMPLING;

TIMING JITTER;

EID: 34548862958     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. N. Abaskharoun et al., "Circuits for On-Chip Sub-Nanosecond Signal Capture and Characterization," IEEE Proc. CICC, 2001.
2. D. Weinlader et al., "An Eight Channel 36Gsample/s CMOS Timing Analyzer," IEEE ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2000.