A library-based synthesis methodology for reversible logic

Microelectronics Journal

Volumn 41, Issue 4, 2010, Pages 185-194

  Saeedi, Mehdi ^a   Sedighi, Mehdi ^a   Saheb Zamani, Morteza ^a  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Binding; Optimization; Reversible logic; Synthesis

Indexed keywords

ASSIGNMENT ALGORITHMS; BENCHMARK FUNCTIONS; BINDING METHODS; BUILDING BLOCKES; DECOMPOSITION ALGORITHM; DISJOINT CYCLE; FOCAL POINTS; GRAPH MATCHING PROBLEMS; INTERMEDIATE FORMATS; LOW COST CIRCUIT; POSTSYNTHESIS; REPRESENTATION MODEL; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC; SYNTHESIS METHODOLOGY; SYNTHESIS OPTIMIZATION;

COST BENEFIT ANALYSIS; LOGIC GATES; OPTIMIZATION; PATTERN MATCHING; SPECIFICATIONS; SYNTHESIS (CHEMICAL);

LOGIC CIRCUITS;

EID: 77950187717     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2010.02.002     Document Type: Article

References (40)

1. Landauer R. Irreversibility and heat generation in the computing process. IBM Journal of Research and Development 5 (1961) 183-191
2. Bennett C. Logical reversibility of computation. IBM Journal 17 6 (1973) 525-532
3. J.M. Rabaey, Low Power Design Essentials, Series on Integrated Circuits and Systems, Springer New York, New York, NY, 2009.
4. J. Stinson, S. Rusu, A 1.5GH third generation itanium 2 processor, in: Design Automation Conference, June 2003, pp. 706-709.
5. V.V. Zhirnov, R.K. Kavin, J.A. Hutchby, G.I. Bourianoff, Limits to binary logic switch scaling-a gedanken model, Proceedings of the IEEE 91(11) (2003) 1934-1939.
6. G. Schrom, Ultra-low-power CMOS technology, Ph.D. Thesis, Technischen Universitat Wien, June 1998.
7. Technology roadmap for semiconductors, 2007.
8. Maslov D., Dueck G.W., and Miller D.M. Techniques for the synthesis of reversible Toffoli networks. ACM Transactions on Design Automation of Electronic Systems 12 4 (2007) 42
9. Nielsen M., and Chuang I. Quantum Computation and Quantum Information (2000), Cambridge University Press
10. Barenco A., Bennett C., Cleve R., DiVincenzo D., Margolus N., Shor P., Sleator T., Smolin J., and Weinfurter H. Elementary gates for quantum computation. APS Physical Review A 52 (1995) 3457-3467
11. Shende V.V., Prasad A.K., Markov I.L., and Hayes J.P. Synthesis of reversible logic circuits. IEEE Transactions on CAD 22 6 (2003) 710-722
12. Hung W.N.N., Song X., Yang G., Yang J., and Perkowski M. Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Transactions on CAD 25 9 (2006) 1652-1663
13. Große D., Wille R., Dueck G.W., and Drechsler R. Exact multiple control Toffoli network synthesis with sat techniques. IEEE Transactions on CAD 28 5 (2009) 703-715
14. M. Saeedi, M. Sedighi, M. Saheb Zamani, A novel synthesis algorithm for reversible circuits, in: IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 65-68.
15. R. Wille, R. Drechsler, BDD-based synthesis of reversible logic for large functions, in: Design Automation Conference, 2009, pp. 270-275.
16. Gupta P., Agrawal A., and Jha N.K. An algorithm for synthesis of reversible logic circuits. IEEE Transactions on CAD 25 11 (2006) 2317-2330
17. Mohammadi M., and Eshghi M. On figures of merit in reversible and quantum logic designs. Quantum Information Processing 8 4 (2009) 297-318
18. Ross M., and Oskin M. Quantum computing. Communications on ACM 51 7 (2008) 12-13
19. Z. Sasanian, M. Saeedi, M. Saheb Zamani, M. Sedighi, A cycle based synthesis algorithm for reversible logic, in: Asia and South Pacific Design Automation Conference, 2009, pp. 745-750.
20. Shende V.V., Bullock S.S., and Markov I.L. Synthesis of quantum logic circuits. IEEE Transactions on CAD 25 6 (2006) 1000-1010
21. Smolin J.A., and Divincenzo D.P. Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Physical Review A 53 (1996) 2855-2856
22. Lee S., Lee S.J., Kim T., Lee J.S., Biamonte J., and Perkowski M. The cost of quantum gate primitives. Journal of Multiple-Valued Logic and Soft Computing 12 5-6 (2006)
23. W.N.N. Hung, X. Song, G. Yang, J. Yang, M. Perkowski, Quantum logic synthesis by symbolic reachability analysis, in: Design Automation Conference, 2004, pp. 838-841.
24. Maslov D., Dueck G.W., Miller D.M., and Negrevergne C. Quantum circuit simplification and level compaction. IEEE Transactions on CAD 27 3 (2008) 436-444
25. Negrevergne C., Mahesh T.S., Ryan C.A., Ditty M., Cyr-Racine F., Power W., Boulant N., Havel T., Cory D.G., and Laflamme R. Benchmarking quantum control methods on a 12-qubit system. Physical Review Letters 96 17 (2006)
26. G. Berkolaiko, J.M. Harrison, M. Novaes, On inequivalent factorizations of a cycle, arXiv:0809.3476 [math.CO], 2008.
27. Hurwitz A. Uber riemannsche flachen mit gegebenen verzweigungspunkten. Mathematische Annalen 39 (1891) 1-60
28. Eidswick J.A. Short factorizations of permutations into transpositions. Discrete Mathematics 73 (1989) 243-293
29. C.M. Springer, Factorizations, trees, and cacti, in: Eighth International Conference on Formal Power Series and Algebraic Combinatorics, 1996, pp. 427-438.
30. Svore K.M., Aho A.V., Cross A.W., Chuang I., and Markov I.L. A layered software architecture for quantum computing design tools. Computer 39 1 (2006) 74-83
31. M. Udrescu, L. Prodan, M. Vlǎdutiu, Using hdls for describing quantum circuits: a framework for efficient quantum algorithm simulation, in: CF '04: Proceedings of the 1st Conference on Computing Frontiers, 2004, pp. 96-110.
32. Balensiefer S., Kregor-Stickles L., and Oskin M. An evaluation framework and instruction set architecture for ion-trap based quantum micro-architectures. SIGARCH Computer Architecture News 33 2 (2005) 186-196
33. M. Whitney, N. Isailovic, Y. Patel, J. Kubiatowicz, Automated generation of layout and control for quantum circuits, in: International Conference on Computing Frontiers, 2007, pp. 83-94.
34. D. Große, R. Wille, G.W. Dueck, R. Drechsler, Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares, in: International Symposium on Multiple Valued Logic, 2008, pp. 214-219.
35. Prasad A.K., Shende V.V., Patel K.N., Markov I.L., and Hayes J.P. Data structures and algorithms for simplifying reversible circuits. Journal on Emerging Technologies in Computing Systems 2 4 (2006)
36. R. Wille, G.W. Große, D. Dueck, R. Drechsler, Reversible logic synthesis with output permutation, in: International Conference on VLSI Design, 2009, 189-194.
37. M. Saeedi, M. Saheb Zamani, M. Sedighi, On the behavior of substitution based reversible circuit synthesis algorithms: investigation and improvement, in: International Symposium on VLSI, vol. 10, 2007, pp. 428-436.
38. M. Saeedi, N. MohammadZadeh, M. Sedighi, M. Saheb Zamani, Evaluation and improvement of quantum synthesis algorithms based on a thorough set of metrics, in: EUROMICRO Conference on Digital System Design Architectures Methods and Tools, 2008, pp. 490-493.
39. V. Kolmogorov, Blossom V: a new implementation of a minimum cost perfect matching algorithm, University College London, 2008.
40. R. Wille, D. Große, L. Teuber, G.W. Dueck, R. Drechsler, Revlib: an online resource for reversible functions and reversible circuits, in: International Symposium on Multiple Valued Logic, 2008, pp. 220-225.