Quantum logic synthesis by symbolic reachability analysis

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 838-841

  Hung, William N N ^a   Song, Xiaoyu ^b   Yang, Guowu ^b   Yang, Jin ^a   Perkowski, Marek ^b  

^a INTEL CORPORATION   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

Formal Verification; Model Checking; Quantum Computing; Reversible Logic; Satisfiability

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COSTS; DATA REDUCTION; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); PROBLEM SOLVING;

FORMAL VERIFICATION; QUANTUM COMPUTING; QUANTUM LOGIC; REVERSIBLE LOGIC;

QUANTUM ELECTRONICS;

EID: 4444351564     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996790     Document Type: Conference Paper

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