A wafer-level 3D integration using bottom-up copper electroplating and hybrid metal-adhesive bonding

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 163-164

  Song, Chongshen ^a   Wang, Zheyao ^a   Tan, Zhimin ^a   Liu, Litian ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ADHESIVE BONDING; ADHESIVE WAFER BONDING; COPPER ELECTROPLATING; HIGH ASPECT RATIO; HYBRID BONDING; POLYMER ADHESIVES; SN BUMPS; THROUGH SILICON VIAS; TWO LAYERS; WAFER-LEVEL 3D INTEGRATION;

ASPECT RATIO; COPPER PLATING; PRESSURE DROP; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; THREE DIMENSIONAL; TIN;

WAFER BONDING;

EID: 70349469835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090374     Document Type: Conference Paper

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