Multi-stack flip chip 3D packaging with copper plated through-silicon vertical interconnection

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 2, Issue , 2005, Pages 384-389

  Hon, Ronald ^a   Ricky Lee, S W ^a   Zhang, Shawn X ^a   Wong, C K ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTROPLATING; FLIP CHIP DEVICES; REACTIVE ION ETCHING; SOFTWARE PROTOTYPING;

DEEP REACTIVE ION ETCHING (DRIE); MULTI-STACK FLIP CHIP 3D PACKAGING; WAFER THINNING;

ELECTRONICS PACKAGING;

EID: 33847330778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. S.W. Ricky Lee, Ronald Hon, Shawn X. D. Zhang, C. K. Wong, "3D Stacked Flip Chip Packaging with Through Silicon Vias and Copper Plating or Conductive Adhesive Filling," Proc. 55th Electronic Components & Technology Conference, Florida, May 31- June 3, 2005, pp. 795-801.
2. th European Microelectronics & Packaging Conference and Exhibition, Friedrichshafen, Germany, June 23-25, 2003.
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4. rd Electronic Components & Technology Conference, New Orleans, LA, May 27-30, 2003, pp. 631-633.
5. Lee, R. A. and Whittaker, D. R., "Laser Created Silicon Vias For Stacking Dies in MCMs," Proc. Electronics Manufacturing Technology Symposium, 1991, pp. 262-265.
6. th International Conference on Electronic Packaging Technology, October 28-30, 2003, pp. 167-170.
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8. th International Conference on Transducers, Solid-State Sensors, Actuators & Microsystems, June 8-12, 2003, pp. 1631-1634.
9. Nguyen, N. T., Boellaard, E. and Pham, N. P., Kutchoukov, V. G., Craciun, G. and Sarro, P. M., "Through-wafer copper electroplating for three-dimensional interconnects," Journal of Micromechanics and Microengineering, 2002 (12), pp. 395-399.