Chip embedded wafer level packaging technology for stacked RF-SiP application

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 305-310

  Chien, Wei ^a   Shen, Li Cheng ^a   Chang, Tao Chih ^a   Chang, Chin Yao ^a   Leu, Fang Jun ^a   Yang, Tsung Fu ^a   Ko, Cheng Ta ^a   Lee, Ching Kuan ^a   Shu, Chao Kai ^a   Lee, Yuan Chang ^a   Shih, Ying Ching ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; INTERCONNECTION NETWORKS; LAMINATING; MICROPROCESSOR CHIPS; SILICON WAFERS; THICKNESS MEASUREMENT;

DIELECTRIC LAYERS; DIGITAL WAFERS; LAMINATION; LASER DRILLING;

CHIP SCALE PACKAGES;

EID: 35348870992     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373814     Document Type: Conference Paper

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