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Volumn , Issue , 2010, Pages 440-445

FinFET SRAM design

Author keywords

[No Author keywords available]

Indexed keywords

FINFET DEVICES; FINFETS; GATED DEVICES; PARAMETER SPACES; SRAM DESIGN; UNIQUE FEATURES;

EID: 77949974205     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2010.88     Document Type: Conference Paper
Times cited : (14)

References (15)
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  • 2
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  • 5
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    • Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications
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    • M.-H. Chiang et al., "Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications," IEEE TED, vol. 55, no 9, Sep. 2008.
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  • 6
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  • 7
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    • Joshi, R.V.1
  • 8
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    • Z. Guo et al., "FinFET-Based SRAM Design," ISLPED., pp. 2-7, Aug. 2005.
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  • 9
    • 2942689838 scopus 로고    scopus 로고
    • FinFET SRAM - device and circuit design considerations
    • H. Ananthan et al., "FinFET SRAM - device and circuit design considerations", ISQED 2004. pp. 511-516
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  • 10
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    • A High Threshold Voltage-Controllable 4T FinFET with an 8.5-nm-Thick Si-Fin Channel
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    • Y. Liu et al., "A High Threshold Voltage-Controllable 4T FinFET with an 8.5-nm-Thick Si-Fin Channel," IEEE Elec. Dev. Lett., Vol. 25, No.7, pp.510-512, July 2004.
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  • 11
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    • R. V. Joshi et al., "FinFET SRAM for high-performance and low-power applications," ESSDERC, pp. 69-72, Sep. 2004.
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  • 12
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  • 13
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  • 14
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.