A new algorithm for simultaneous gate sizing and threshold voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 2, 2010, Pages 223-234

  Liu, Yifang ^a   Hu, Jiang ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Algorithms; Circuit optimization

Indexed keywords

BENCHMARK CIRCUIT; BI-DIRECTIONAL; CIRCUIT OPTIMIZATION; CIRCUIT TIMING; COMBINATORIAL APPROACH; CONTINUOUS OPTIMIZATION; DISCRETIZATIONS; EXISTING METHOD; GATE SIZING; JOINT RELAXATION; LOCAL OPTIMA; POWER DISSIPATION; POWER OPTIMIZATION; TIMING CONSTRAINTS;

ALGORITHMS; ELECTRIC CURRENTS; GATES (TRANSISTOR); HEURISTIC METHODS; OPTIMIZATION; THRESHOLD VOLTAGE; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 76649089315     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2035575     Document Type: Conference Paper

References (24)

1. J. Fishburn and A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. Int. Conf. Comput.-Aided Design, 1985, pp. 326-328.
2. C. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE Trans. Comput.- Aided Design, vol.18, no.7, pp. 1014-1025, 1999.
3. O. Coudert, "Gate sizing for constrained delay/power/area optimization," IEEE Trans. Very Large Scale Integr., vol.5, no.4, pp. 465-472, Dec. 1997.
4. P. K. Chan, "Algorithms for library-specific sizing of combinational logic," in Proc. Design Autom. Conf., 1990, pp. 353-356.
5. S. Hu, M. Ketkar, and J. Hu, "Gate sizing for cell library based designs," in Proc. Design Autom. Conf., 2007, pp. 847-852.
6. L. Wei, Z. Chen, K. Roy, and V. De, "Design and optimization of dual threshold circuits for low voltage low power application," IEEE Trans. Very Large Scale Integr. Syst., vol.7, no.1, pp. 16-24, Mar. 1999.
7. V. Sundararajan and K. K. Parhi, "Low power synthesis of dual threshold voltage CMOS circuits," in Proc. Int. Symp. Low Power Electron. Design, 1999, pp. 139-144.
8. V. Khandelwal, A. Davoodi, and A. Srivastava, "Simultaneous Vt selection and assignment for leakage optimization," IEEE Trans. Very Large Scale Integr., vol.13, no.6, pp. 762-765, 2005.
9. M. Ketkar and S. S. Sapatnekar, "Stand-by power optimization via transistor sizing and dual threshold voltage assignment," in Proc. Int. Conf. Comput.-Aided Design, 2002, pp. 375-378.
10. D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer, "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization," in Proc. Int. Symp. Low Power Electron. Design, 2003, pp. 158-162.
11. D. G. Chinnery and K. Keutzer, "Linear programming for sizing, Vth and Vdd assignment," in Proc. Int. Symp. Low Power Electron. Design, 2005, pp. 149-154.
12. D. G. Chinnery, B. Thompson, M. Orshansky, and K. Keutzer, "Power minimization with multiple supply voltages and multiple threshold voltages," in Proc. Semiconductor Res. Corporation Techcon, 2003.
13. S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Balaauw, and V. Zolotov, "Discrete Vt assignment and gate sizing using a self-snapping continuous formulation," in Proc. Int. Conf. Comput.-Aided Design, 2005, pp. 704-710.
14. S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, and D. Blaauw, "Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing," in Proc. Design Autom. Conf., 1999, pp. 436-441.
15. H. Chou, Y. Wang, and C. Chen, "Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian relaxation," in Proc. Asia South Pacific Design Autom. Conf., 2005, pp. 381-386.
16. T.-H. Wu, L. Xie, and A. Davoodi, "A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing," in Proc. Int. Symp. Low Power Electron. Design, 2008, pp. 45-50.
17. K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar, "A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]," IEEE Trans. Compu.-Aided Design, vol.13, no.6, pp. 779-788, 2000.
18. S. Roy, W. Chen, and C. C. Chen, "ConvexFit: An optimal minimumerror convex fitting and smoothing algorithm with application to gatesizing," in Proc. Int. Conf. Comput.-Aided Design, 2005, pp. 196-204.
19. J. Lillis, C. K. Cheng, and T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE J. Solid- State Circuits, vol.31, no.3, pp. 437-447, Mar. 1996.
20. C. L. Ratzlaff, N. Gopal, and L. T. Pillage, "RICE: Rapid interconnect circuit evaluator," in Proc. Design Autom. Conf., 1999, pp. 555-560.
21. J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance of RC interconnect," IEEE Trans. Comput.-Aided Design, vol.13, no.12, pp. 1526-1535, 1994.
22. M. Bazaraa, H. Sherali, and C. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. New York: Wiley, 2003.
23. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Snagiovanni, "SIS: A system for sequential circuit synthesis," Electron. Res. Lab., Univ. California, Berkeley, CA, Mem. UCB/ERL M92/41, May 1992.
24. CPMO-constrained placement by multilevel optimization [Online]. Available: http://ballade.cs.ucla.edu/cpmo