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Volumn 26, Issue 2, 2009, Pages 34-43

Incremental verification with error detection, diagnosis, and visualization

Author keywords

[No Author keywords available]

Indexed keywords

INCREMENTAL VERIFICATION; POTENTIAL ERRORS; SIMILARITY FACTORS; SYNTHESIS OPTIMIZATION; VERIFICATION SYSTEMS;

EID: 66149092713     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.38     Document Type: Article
Times cited : (4)

References (9)
  • 1
    • 66149137532 scopus 로고    scopus 로고
    • Future of Chip Design Revealed at ISPD
    • 17 Apr. 2008;
    • R.C. Johnson, "Future of Chip Design Revealed at ISPD," EE Times 17 Apr. 2008; http://www.eetimes.com/ showArticle.jhtml?articleID=207400313.
    • EE Times
    • Johnson, R.C.1
  • 2
    • 0026005478 scopus 로고
    • Retiming Synchronous Circuitry
    • C.E. Leiserson and J.B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, nos. 1-6, 1991, pp. 5-35.
    • (1991) Algorithmica , vol.6 , Issue.1-6 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 3
    • 66149089488 scopus 로고    scopus 로고
    • Conformal Finds DC/PhysOpt Was Missing 40 DFFs!
    • ESNUG (E-mail Synopsys Users Group) 464, item, Mar
    • "Conformal Finds DC/PhysOpt Was Missing 40 DFFs!" ESNUG (E-mail Synopsys Users Group) 464, item 4, 30 Mar. 2007.
    • (2007) , vol.4 , Issue.30
  • 4
    • 66149153001 scopus 로고    scopus 로고
    • I. Chayut, Next-Generation Multimedia Designs: Verification Needs, 43rd Design Automation Conf. (DAC 06), ACM, 2006; http://videos.dac.com/43rd/23_2/23-2.html.
    • I. Chayut, "Next-Generation Multimedia Designs: Verification Needs," 43rd Design Automation Conf. (DAC 06), ACM, 2006; http://videos.dac.com/43rd/23_2/23-2.html.
  • 5
    • 34547147084 scopus 로고    scopus 로고
    • SAT Sweeping with Local Observability Don't-Cares
    • ACM Press
    • Q. Zhu et al., "SAT Sweeping with Local Observability Don't-Cares," Proc. 43rd Design Automation Conf. (DAC 06), ACM Press, 2006, pp. 229-234.
    • (2006) Proc. 43rd Design Automation Conf. (DAC 06) , pp. 229-234
    • Zhu, Q.1
  • 7
    • 34548124930 scopus 로고    scopus 로고
    • InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization
    • IEEE CS Press
    • K.-H. Chang et al., "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization," Proc. 8th Int'l Symp. Quality Electronic Design (ISQED 07), IEEE CS Press, 2007, pp. 487-492.
    • (2007) Proc. 8th Int'l Symp. Quality Electronic Design (ISQED 07) , pp. 487-492
    • Chang, K.-H.1
  • 8
    • 66149134384 scopus 로고    scopus 로고
    • Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, release 51205;
    • Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification," release 51205; http:// www.cad.eecs.berkeley.edu/~alanmi/abc.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.