An efficient tile-based ECO router using routing graph reduction and enhanced global routing flow

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 2, 2007, Pages 345-357

  Li, Yih Lang ^a,b   Li, Jin Yih ^c   Chen, Wen Bin ^d  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d Global Unichip   (Taiwan)

Author keywords

Deep submicrometer; Detailed routing; Engineering change order (ECO) routing; Global routing; Gridless routing; Layout; Physical design; System on chip

Indexed keywords

DEEP SUBMICROMETER; DETAILED ROUTING; ENGINEERING CHANGE ORDER ROUTING; GLOBAL ROUTING; GRIDLESS ROUTING; SYSTEM-ON-CHIP;

COMPUTATIONAL METHODS; GRAPH THEORY; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; OPTIMIZATION; WAVE PROPAGATION;

ROUTERS;

EID: 33846576611     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.883923     Document Type: Conference Paper

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