An ECO routing algorithm for eliminating coupling-capacitance violations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 9, 2006, Pages 1754-1761

  Xiang, Hua ^a,b   Chao, Kai Yuan ^a,c   Wong, Martin D F ^a,d  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c INTEL CORPORATION   (United States)

^d University of Illinois at Urbana Champaign   (United States)

Author keywords

Coupling capacitance; Engineering change order (ECO); Routing

Indexed keywords

COUPLING CAPACITANCE; COUPLINGCAPACITANCE VIOLATION ELIMINATION (CVE); ENGINEERING CHANGE ORDER (ECO); MULTIPLE LAYER ROUTING;

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; COUPLED CIRCUITS; INTEGRATED CIRCUITS; PROBLEM SOLVING; ROUTERS;

CAPACITANCE;

EID: 33748114506     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.857396     Document Type: Article

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