A watt-level stacked-FET linear power amplifier in silicon-on-insulator CMOS

IEEE Transactions on Microwave Theory and Techniques

Volumn 58, Issue 1, 2010, Pages 57-64

  Pornpromlikit, Sataporn ^a   Jeong, Jinho ^b   Presti, Calogero D ^a   Scuderi, Antonino ^c   Asbeck, Peter M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Kwangwoon University   (South Korea)

^c STMICROELECTRONICS   (Italy)

Author keywords

CMOS; Code division multiple access (CDMA); Power amplifier (PA); Silicon on insulator (SOI); Stacked transistors; Wideband code division multiple access (WCDMA)

Indexed keywords

ADJACENT CHANNEL LEAKAGE RATIOS; ADJACENT CHANNEL POWER RATIO; BREAKDOWN VOLTAGE; CMOS; GAAS; GIGAHERTZ FREQUENCIES; IN-PHASE; LINEAR POWER AMPLIFIERS; MAXIMUM POWER; MODULATED SIGNAL; MOSFETS; OUTPUT POWER; OUTPUT VOLTAGE SWINGS; SATURATED OUTPUT POWER; SILICON-ON-INSULATOR CMOS; SILICON-ON-INSULATORS; SINGLE STAGE; SMALL-SIGNAL GAIN; SOI CMOS; STACKED TRANSISTORS; SUBMICROMETERS; SUPPLY VOLTAGES; WIDEBAND CODE DIVISION MULTIPLE ACCESS;

BROADBAND AMPLIFIERS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; FIELD EFFECT TRANSISTORS; HETEROJUNCTION BIPOLAR TRANSISTORS; MESFET DEVICES; MICROSENSORS; POWER AMPLIFIERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 75449094411     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2009.2036323     Document Type: Article

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