Effect of lattice mismatch on gate lag in high quality InAlN/AlN/GaN HFET structures

Physica Status Solidi (A) Applications and Materials Science

Volumn 207, Issue 1, 2010, Pages 211-216

  Leach, J H ^a   Wu, M ^a   Ni, X ^a   Li, X ^a   Ozgur U ^a   Morkoc H ^a  

^a Virginia Commonwealth University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOWING PARAMETERS; GATE LAG; GATE LENGTH; HETEROJUNCTION FIELD EFFECT TRANSISTOR; HIGH QUALITY; LARGE BAND; LATTICE MATCHING; LATTICE PARAMETERS; LATTICE-MATCHED; LATTICE-MATCHING CONDITIONS; MAXIMUM DRAIN CURRENT; MISFIT STRAINS; PIEZOELECTRIC CHARGE; PULSED MODE; RECENT PROGRESS; STRAIN-FREE;

CUTOFF FREQUENCY; DRAIN CURRENT; GALLIUM ALLOYS; GALLIUM NITRIDE; HETEROJUNCTIONS; LATTICE MISMATCH;

FIELD EFFECT TRANSISTORS;

EID: 74549117357     PISSN: 18626300     EISSN: 18626319     Source Type: Journal    
DOI: 10.1002/pssa.200925362     Document Type: Article

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