Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 10, 2004, Pages 1985-1997

  Chang, Chip Hong ^a   Gu, Jiangmin ^a   Zhang, Mingyan ^a  

^a Sch Elec Electron Eng   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL ARITHMETIC; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MULTIPLYING CIRCUITS; TRANSISTORS;

ARITHMETIC CIRCUITS; DIGITAL MULTIPLIERS;

CMOS INTEGRATED CIRCUITS;

EID: 7444250357     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.835683     Document Type: Article

References (19)

1. H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates," IEEE Trans. Circuits Syst. II, vol. 49, pp. 25-30, Jan. 2002.
2. J. Gu and C. H. Chang, "Low voltage, low-power (5:2) compressor cell for fast arithmetic circuits," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, vol. 2, 2003, pp. 661-664.
3. J. Gu, "Ultra Low-voltage, low-power 4-2 compressor for high speed multiplications," in Proc. 36th IEEE Int. Symp. Circuits Systems, Bangkok, Thailand, May 2003.
4. J. E. Gunn, K. S. Barron, and W. Ruczczyk, "A low-power DSP corebased software radio architecture," IEEE J. Select. Areas Commun., vol. 17, no. 4, pp. 574-590, 1999.
5. S. F. Hsiao, M. R. Jiang, and J. S. Yeh, "Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers," Electron. Lett., vol. 34, no. 4, pp. 341-343, 1998.
6. O. Kwon, K. Nowka, and E. E. Swartzlander, "A 16-bit × 16-bit MAC design using fast 5:2 compressor," in Proc. IEEE Int. Conf. Application-Specific Systems, Architectures, Processors, 2000, pp. 235-243.
7. M. Margala and N. G. Durdle, "Low-power low-voltage 4-2 compressors for VLSI applications," in Proc. IEEE Alessandro Volta Memorial Workshop Low-Power Design, 1999, pp. 84-90.
8. M. Mehta, V. Parmar, and E. Swartzlander Jr., "High-speed multiplier design using multi-input counter and compressor circuits," in Proc. 10th IEEE Symp. Computer Arithmetic, June 1991, pp. 43-50.
9. C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time-power tradeoffs in parallel adders," IEEE Trans. Circuits Syst. II, vol. 43, pp. 689-702, Oct. 1996.
10. K. Prasad and K. K. Parhi, "Low-power 4-2 and 5-2 compressors," in Proc. of the 35th Asilomar Conf. on Signals, Systems and Computers, vol. 1, 2001, pp. 129-133.
11. D. Radhakrishnan, "Low-voltage low-power CMOS full adder," Proc. Inst. Elect. Eng., Circuits Devices Syst., vol. 148, no. 1, pp. 19-24, 2001.
12. D. Radhakrishnan and A. P. Preethy, "Low-power CMOS pass logic 4-2 compressor for high-speed multiplication," in Proc. 43rd IEEE Midwest Symp. Circuits Syst., vol. 3, 2000, pp. 1296-1298.
13. A. M. Shams and M. A. Bayoumi, "A structured approach for designing low-power adders," in Proc. 31st Asilomar Conf. Signals, Syst. Computers, vol. 1, 1997, pp. 757-761.
14. A. M. Shams, "A novel high-performance CMOS 1-bit full-adder cell," IEEE Trans. Circuits Sys. II, vol. 47, pp. 478-481, May 2000.
15. A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. VLSI Syst., vol. 10, pp. 20-29, Jan. 2002.
16. P. J. Song and G. De Micheli, "Circuit and architecture trade-offs for high-speed multiplication," IEEE J. Solid-State Circuits, vol. 26, pp. 1184-1198, Sept. 1991.
17. T. K. K. Tsang and M. N. El-Gamal, "Gain and frequency controlled sub-1 V 5.8 GHz CMOS LNA," in Proc. IEEE Int. Symp. Circuits Systems, vol. 4, 2002, pp. 795-798.
18. Z. Wang, G. A. Jullien, and W. C. Miller, "A new design technique for column compression multipliers," IEEE Trans. Comput., vol. 44, pp. 962-970, Aug. 1995.
19. R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.