Low-power 4-2 and 5-2 compressors

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2001, Pages 129-133

  Prasad, Karuna ^a   Parhi, Keshab K ^b  

^a Infineon Technologies MorphICs Inc   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; POWER SUPPLY CIRCUITS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; VLSI CIRCUITS;

BINARY MULTIPLIERS; LOW POWER COMPRESSORS; POWER CONSUMPTION;

MULTIPLYING CIRCUITS;

EID: 0035575269     PISSN: 10586393     EISSN: None     Source Type: Journal    
DOI: 10.1109/ACSSC.2001.986892     Document Type: Article

References (7)

1. A 3.8ns cmos 16×16-b multiplier using complementary pass-transistor logic
2. Low power circuit implementation for partial-product addition using pass-transistor logic
3. A 4.4-ns cmos 54×54-b multiplier using pass-transistor multiplexer
4. A 16-bit × 16-bit mac design using fast 5:2 compressors
5. New efficient designs for xor and xnor functions on the transistor level