Low power CMOS pass logic 4-2 compressor for high-speed multiplication

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages 1296-1298

  Radhakrishnan, D ^a   Preethy, A P ^b  

^a STATE UNIVERSITY OF NEW YORK   (United States)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC DESIGN; LOGIC GATES; MULTIPLYING CIRCUITS;

CMOS PASS LOGIC; COMPLEMENTARY PASS TRANSISTOR LOGIC; POWER DISSIPATION;

LOGIC CIRCUITS;

EID: 0034464460     PISSN: 15483746     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSCAS.2000.951453     Document Type: Article

References (14)

1. Designing low power CMOS
2. A suggestion for a fast multiplier
3. A 15nS 32×32-bit CMOS multiplier with an improved parallel structure
4. A 10-ns 54X54-b parallel structured full array multiplier with 0.5μm CMOS technology
5. A 3.8-ns CMOS 16X16-b multiplier using complementary pass-transistor logic
6. TWTXBB: A low latency, high throughput multiplier architecture using a new 4-2 compressor
7. 4-2 compressor with complementary pass-transistor logic
8. A 4.4-ns CMOS 54X54-b multiplier using pass-transistor multiplier
9. Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
10. Low-power low-voltage 4-2 compressors for VLSI applications
11. A structured approach for designing low power adders
12. Low voltage CMOS full adder cells
13. Formal design procedures for pass transistor switching circuits
14. Design of CMOS circuits