A novel high-Performance CMOS 1-bit full-adder cell

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 5, 2000, Pages 478-481

  Shams, Ahmed M ^a   Bayoumi, Magdy A ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

Binary addition; Full adder; High speed; Low power

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LOGIC GATES;

FULL ADDER CELL; PASS TRANSISTORS; POWER CONSUMPTION; TRANSMISSION GATES;

ADDERS;

EID: 0033730819     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.842117     Document Type: Article

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