-
1
-
-
0003397202
-
-
Boston, U. S. A., Kluwer Academic Publishers
-
Bellaouar, A. and Elmasry, M. I., Low-Power Digital VLSI Design-Circuits and Systems, Boston, U. S. A., Kluwer Academic Publishers, 1995.
-
(1995)
Low-Power Digital VLSI Design-Circuits and Systems
-
-
Bellaouar, A.1
Elmasry, M.I.2
-
2
-
-
0004173639
-
-
Boston, U. S. A., Kluwer Academic Publishers
-
Rabaey, J. M., and Pedram M., editors, Low Power Design Methodologies, Boston, U. S. A., Kluwer Academic Publishers, 1996.
-
(1996)
Low Power Design Methodologies
-
-
Rabaey, J.M.1
Pedram, M.2
-
4
-
-
0028405787
-
4-2 compressor with complementary pass-transistor logic
-
April
-
Kanie, Y. and Kubota, Y., 4-2 Compressor with Complementary Pass-Transistor Logic, IEICE Transactions on Electronics, vol. E77-C, no. 4, pp. 647-649, April 1994.
-
(1994)
IEICE Transactions on Electronics
, vol.E77-C
, Issue.4
, pp. 647-649
-
-
Kanie, Y.1
Kubota, Y.2
-
5
-
-
0032545853
-
Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
-
19th February
-
Hsiao, S.-F., Jiang, M.-R., and Yeh, J.-S., Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers, Electronics Letters, vol. 34, no. 4, pp. 341-343, 19th February 1998.
-
(1998)
Electronics Letters
, vol.34
, Issue.4
, pp. 341-343
-
-
Hsiao, S.-F.1
Jiang, M.-R.2
Yeh, J.-S.3
-
6
-
-
0344000306
-
Novel low-voltage low-power full-swing BiNMOS logic gate
-
May
-
Margala, M., and Durdle, N. G., Novel low-voltage low-power full-swing BiNMOS logic gate. International Journal of Electronics, vol. 84, no. 5, pp. 487-498, May 1998.
-
(1998)
International Journal of Electronics
, vol.84
, Issue.5
, pp. 487-498
-
-
Margala, M.1
Durdle, N.G.2
-
7
-
-
0032119164
-
1. 2V full-swing BiDPL logic gate
-
July
-
Margala, M., and Durdle, N. G., 1. 2V full-swing BiDPL logic gate. Microelectronics Journal, vol. 29, no. 7, pp. 491-498, July 1998.
-
(1998)
Microelectronics Journal
, vol.29
, Issue.7
, pp. 491-498
-
-
Margala, M.1
Durdle, N.G.2
-
8
-
-
0027694895
-
A 1. 5-ns 32-b CMOS alu in double pass-transistor logic
-
November
-
Suzuki, M., Ohkubo, N., Shinbo, T., Yamanaka, T., Shimizu, A., Sasaki, K., and Nakagome, Y., A 1. 5-ns 32-b CMOS ALU in Double Pass-Transistor Logic. IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1145-1151, November 1993.
-
(1993)
IEEE Journal of Solid-State Circuits
, vol.28
, Issue.11
, pp. 1145-1151
-
-
Suzuki, M.1
Ohkubo, N.2
Shinbo, T.3
Yamanaka, T.4
Shimizu, A.5
Sasaki, K.6
Nakagome, Y.7
-
9
-
-
0026925486
-
A 54 x 54-b regularly structured tree multiplier
-
December
-
Goto, G., Sato, T., Nakajima, M, and Sukeruma, T., A 54 x 54-b Regularly Structured Tree Multiplier. IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1229-1236, December 1992.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, Issue.12
, pp. 1229-1236
-
-
Goto, G.1
Sato, T.2
Nakajima, M.3
Sukeruma, T.4
-
10
-
-
0026136710
-
A 10-ns 54 x 54-b parallel full array multiplier with 0. 5-?M CMOS technology
-
June
-
Mori, J., Nagamatsu, M., Hirano, M., Tanaka, S., Noda, M., Toyoshima, Y., Hashimoto, K., Hayashida, H., and Maeguchi, K., A 10-ns 54 x 54-b Parallel Full Array Multiplier with 0. 5-?m CMOS Technology. IEEE Journal of Solid-State Circuits, vol. 26, no. 6, pp. 600-606, June 1991.
-
(1991)
IEEE Journal of Solid-State Circuits
, vol.26
, Issue.6
, pp. 600-606
-
-
Mori, J.1
Nagamatsu, M.2
Hirano, M.3
Tanaka, S.4
Noda, M.5
Toyoshima, Y.6
Hashimoto, K.7
Hayashida, H.8
Maeguchi, K.9
|