Quantification of drain extension leakage in a scaled bulk germanium PMOS technology

IEEE Transactions on Electron Devices

Volumn 56, Issue 12, 2009, Pages 3115-3122

  Eneman, Geert ^a,b,c   De Jaeger, Brice ^a   Simoen, Eddy ^a   Brunco, David P ^d   Hellings, Geert ^a,b,e   Mitard, Jérôme ^a   De Meyer, Kristin ^a,b   Meuris, Marc ^a   Heyns, Marc M ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c RESEARCH FOUNDATION FLANDERS FWO   (Belgium)

^d INTEL CORPORATION   (United States)

^e Institute for the Promotion of Innovation By Science and Technology in Flanders   (Belgium)

Author keywords

Germanium; Halo implant; Leakage current; MOSFETs; P+ n junctions

Indexed keywords

BAND TO BAND TUNNELING; BULK GERMANIUM; DRAIN EXTENSIONS; DRAIN LEAKAGE; GATE-LENGTH; HALO IMPLANTS; LEAKAGE COMPONENTS; MOSFETS; PMOS TECHNOLOGY; SUPPLY VOLTAGES; THERMAL SENSITIVITY;

ELECTRIC FIELDS; LEAKAGE CURRENTS;

GERMANIUM;

EID: 73849134669     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2033156     Document Type: Article

References (30)

1. H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozlowski, S. Steen, S. Cordes, H.-S. Wong, E. Jones, and W. Haensch, "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," in IEDM Tech. Dig., 2002, pp. 441-444.
2. C. O. Chui, H. Kim, D. Chi, B. Triplett, P. McIntyre, and K. Saraswat, "A sub-400 degrees C germanium MOSFET technology with high-? dielectric and metal gate," in IEDM Tech. Dig., 2002, pp. 437-440.
3. M. Lee, C. Leitz, Z. Cheng, A. Pitera, T. Langdo, M. Currie, G. Taraschi, E. Fitzgerald, and D. Antoniadis, "Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si1-xGex/Si virtual substrates," Appl. Phys. Lett., vol. 79, no. 20, pp. 3344-3346, Nov. 2001.
4. D. Kuzum, A. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. McVittie, P. Pianetta, P. Mclntyre, and K. Saraswat, "Interface-engineered Ge (100) and (111), N-and P-FETs with high mobility," in IEDM Tech. Dig., 2007, pp. 723-726.
5. A. Ritenour, A. Khakifirooz, D. Antoniadis, R. Lei, W. Tsai, A. Dimoulas, G. Mavrou, and Y. Panayiotatos, "Subnanometerequivalent-oxide-thickness germanium p-metal-oxide-semiconductor field effect transistors fabricated using molecular-beam-deposited high-k/metal gate stack," Appl. Phys. Lett., vol. 88, no. 13, pp. 132 107-1-132 107-3, Mar. 2006.
6. G. Nicholas, B. De Jaeger, D. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, and M. Heyns, "High-performance deep submicron Ge pMOSFETs with halo implants," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2503-2511, Sep. 2007.
7. E. Batail, S. Monfray, C. Tabone, O. Kermarrec, J. Damlencourt, P. Gautier, G. Rabille, C. Arvet, N. Loubet, Y. Campidelli, J. Hartmann, A. Pouydebasque, V. Delaye, C. L. Royer, G. Ghibaudo, T. Skotnicki, and S. Deleonibus, "Localized ultra-thin GeOI: An innovative approach to Germanium channel MOSFETs on bulk Si substrates," in IEDM Tech. Dig., 2008, pp. 397-400.
8. G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. Heyns, and K. De Meyer, "High performance 70-nm germanium pMOSFETs with boron LDD implants," IEEE Electron Device Lett., vol. 30, no. 1, pp. 88-90, Jan. 2009.
9. J. Mitard, B. De Jaeger, F. Leys, G. Hellings, K. Martens, G. Eneman, D. Brunco, R. Loo, J. Lin, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, C. Yu, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, and M. Heyns, "Record Ion/Ioff performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability," in IEDM Tech. Dig., 2008, pp. 873-876.
10. T. Yamamoto, Y. Yamashita, M. Harada, N. Taoka, K. Ikeda, K. Suzuki, O. Kiso, N. Sugiyama, and S. Takagi, "High performance 60 nm gate length germanium p-MOSFETs with Ni germanide metal source/drain," in IEDM Tech. Dig., 2006, pp. 1041-1043.
11. Y. Kamata, "High-k/Ge MOSFETs for future nanoelectronics," Mater. Today, vol. 11, no. 1/2, pp. 30-38, Jan./Feb. 2008.
12. C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, "Germanium n-type shallow junction activation dependences," Appl. Phys. Lett., vol. 87, no. 9, pp. 091 909-1-091 909-3, Aug. 2005.
13. D. Brunco, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesmans, J. Van Steenbergen, P. Mertens, M. Meuris, and M. Heyns, "Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance," J. Electrochem. Soc., vol. 155, no. 7, pp. H552-H561, 2008.
14. A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. Kim, "Leakage power analysis and reduction for nanoscale circuits," IEEE Micro, vol. 26, no. 2, pp. 68-80, Mar./Apr. 2006.
15. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
16. D. Kim, T. Krishnamohan, L. Smith, H.-S.Wong, and K. Saraswat, "Band to band tunneling study in high mobility materials: III-V, Si, Ge and strained SiGe," in Proc. 65th Device Res. Conf., 2007, pp. 57-58.
17. T. Krishnamohan and K. Saraswat, "High mobility Ge and III-V materials and novel device structures for high performance nanoscale MOSFETS," in Proc. 38th ESSDERC, 2008, pp. 38-46.
18. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. Saraswat, "High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: Experiments," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 990-999, May 2006.
19. C. Le Royer, B. Vincent, L. Clavelier, J.-F. Damlencourt, C. Tabone, P. Batude, D. Blachier, R. Truche, Y. Campidelli, Q. Nguyen, S. Cristoloveanu, S. Soliveres, G. Le Carval, F. Boulanger, T. Billon, D. Bensahel, and S. Deleonibus, "High-? and metal-gate pMOSFETs on GeOI obtained by Ge enrichment: Analysis of ON and OFF performances," IEEE Electron Device Lett., vol. 29, no. 6, pp. 635-637, Jun. 2008.
20. G. Eneman, M. Wiot, A. Brugere, O. Casain, S. Sonde, D. Brunco, B. De Jaeger, A. Satta, G. Hellings, K. De Meyer, C. Claeys, M. Meuris, M. Heyns, and E. Simoen, "Impact of donor concentration, electric field, and temperature effects on the leakage current in germanium p + /n junctions," IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2287-2296, Sep. 2008.
21. J.-H. Park, D. Kuzum, M. Tada, and K. Saraswat, "High performance germanium N + /P and P + /N junction diodes formed at low temperature (= 380 degrees C) using metal-induced dopant activation," Appl. Phys. Lett., vol. 93, no. 19, pp. 193 507-1-193 507-3, Nov. 2008.
22. R. Duffy, A. Heringa, J. Loo, E. Augendre, S. Severi, and G. Curatola, "Low-leakage ultra-scaled junctions in MOS devices; from fundamentals to improved device performance," ECS Trans., vol. 3, no. 2, pp. 19-33, 2006.
23. 2 structures," Electrochem. Solid-State Lett., vol. 11, no. 2, pp. H39-H41, Feb. 2008.
24. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153-158, Mar. 2005.
25. Sentaurus Process Reference Manual, 2006. X-2006.06 ed
26. Taurus Medici User Guide, 2007. A-2007.12 ed
27. ITRS Roadmap for Semiconductors, ITRS 2007 Edition, Process Integration, Devices and Structures. [Online]. Available: http://www.itrs. net/Links/2007ITRS/Home2007.htm
28. G. Eneman, E. Simoen, R. Yang, B. De Jaeger, G. Wang, J. Mitard, G. Hellings, D. P. Brunco, R. Loo, K. De Meyer, M. Caymax, C. Claeys, M. Meuris, and M. Heyns, "Defects, junction leakage and electrical performance of Ge pFET devices," ECS Trans., vol. 19, no. 1, pp. 195-205, Jan. 2009.
29. E. Simoen, S. Sonde, C. Claeys, A. Satta, B. De Jaeger, R. Todi, and M. Meuris, "Processing factors impacting the leakage current and flicker noise of germanium p + /-n junctions on silicon substrates," J. Electrochem. Soc., vol. 155, no. 3, pp. 145-150, Mar. 2008.
30. S. M. Sze, Physics of Semiconductor Devices. Hoboken, NJ: Wiley, 1981.