Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 27, Issue 6, 2009, Pages 3153-3157

  Li, Xu ^a   Hill, Richard J W ^a,b   Longo, Paolo ^a   Holland, Martin C ^a   Zhou, Haiping ^a   Thoms, Stephen ^a   MacIntyre, Douglas S ^a   Thayne, Iain G ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL DIMENSION; DIELECTRIC DEPOSITION; DRY-ETCH; ENHANCEMENT MODES; FULLY SELF-ALIGNED; GAAS; GATE LENGTH; LIFT-OFF PROCESS; LOW DAMAGES; METAL GATE STACK; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; MOSFETS; PROCESS FLOWS; SIDEWALL SPACER;

DIELECTRIC DEVICES; GADOLINIUM; GALLIUM ALLOYS; ION BEAMS; METALS; MOSFET DEVICES; SEMICONDUCTING GALLIUM; SILICON NITRIDE;

FIELD EFFECT TRANSISTORS;

EID: 72849148574     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.3256624     Document Type: Conference Paper

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