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Volumn 85, Issue 5-6, 2008, Pages 996-999

A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs

Author keywords

Damage; Etch; GaxGdyOz; GaAs; III V MOSFETs; RIE; Si3N4; Sidewall spacer

Indexed keywords

CHEMICAL VAPOR DEPOSITION; DRAIN CURRENT; INDUCTIVELY COUPLED PLASMA; REACTIVE ION ETCHING; SEMICONDUCTING SILICON; SILICON NITRIDE;

EID: 44149114531     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.12.064     Document Type: Article
Times cited : (13)

References (12)
  • 7
    • 0031376844 scopus 로고    scopus 로고
    • M. Goss, R. Thornburg, in: Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Cambridge, USA, 10-12 September, 1997, p. 228.
    • M. Goss, R. Thornburg, in: Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Cambridge, USA, 10-12 September, 1997, p. 228.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.