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Volumn 85, Issue 5-6, 2008, Pages 996-999
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A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs
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Author keywords
Damage; Etch; GaxGdyOz; GaAs; III V MOSFETs; RIE; Si3N4; Sidewall spacer
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Indexed keywords
CHEMICAL VAPOR DEPOSITION;
DRAIN CURRENT;
INDUCTIVELY COUPLED PLASMA;
REACTIVE ION ETCHING;
SEMICONDUCTING SILICON;
SILICON NITRIDE;
DRAIN RESISTANCE;
ELECTROSTATIC INTEGRITY;
SELF-ALIGNMENT;
MOSFET DEVICES;
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EID: 44149114531
PISSN: 01679317
EISSN: None
Source Type: Journal
DOI: 10.1016/j.mee.2007.12.064 Document Type: Article |
Times cited : (13)
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References (12)
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