-
1
-
-
27144503350
-
Bridging dimensions: Demultiplexing ultrahigh density nanowire circuits
-
R. Beckman et al. Bridging dimensions: demultiplexing ultrahigh density nanowire circuits. Science, 310(5747):465-468, 2005.
-
(2005)
Science
, vol.310
, Issue.5747
, pp. 465-468
-
-
Beckman, R.1
-
2
-
-
54949085010
-
Variability-aware design of multi-level logic decoders for nanoscale crossbar memories
-
Nov
-
M. H. Ben Jamaa et al. Variability-aware design of multi-level logic decoders for nanoscale crossbar memories. Transactions on Computer-Aided Design, IEEE, 27(11):2053-2067, Nov. 2008.
-
(2008)
Transactions on Computer-Aided Design, IEEE
, vol.27
, Issue.11
, pp. 2053-2067
-
-
Ben Jamaa, M.H.1
-
4
-
-
47749098936
-
The multi-spacer patterning technique: A non-lithographic technique for terascale integration
-
July
-
G. F. Cerofolini, P. Amato, and E. Romano. The multi-spacer patterning technique: a non-lithographic technique for terascale integration. Semiconductor Science Technology, 23(7):075020-+, July 2008.
-
(2008)
Semiconductor Science Technology
, vol.23
, Issue.7
-
-
Cerofolini, G.F.1
Amato, P.2
Romano, E.3
-
5
-
-
0036494144
-
A spacer patterning technology for nanoscale CMOS
-
March
-
Y.-K. Choi, T.-J. King, and C. Hu. A spacer patterning technology for nanoscale CMOS. Electron Devices, IEEE Transactions on, 49(3):436-441, March 2002.
-
(2002)
Electron Devices, IEEE Transactions on
, vol.49
, Issue.3
, pp. 436-441
-
-
Choi, Y.-K.1
King, T.-J.2
Hu, C.3
-
7
-
-
2442617450
-
Stochastic assembly of sublithographic nanoscale interfaces
-
A. DeHon, P. Lincoln, and J. Savage. Stochastic assembly of sublithographic nanoscale interfaces. IEEE Transactions on Nanotechnology, 2(3):165-174, 2003.
-
(2003)
IEEE Transactions on Nanotechnology
, vol.2
, Issue.3
, pp. 165-174
-
-
DeHon, A.1
Lincoln, P.2
Savage, J.3
-
9
-
-
33645013400
-
Assembling nanoscale circuits with randomized connections
-
T. Hogg, Y. Chen, and P. Kuekes. Assembling nanoscale circuits with randomized connections. IEEE Transactions on Nanotechnology, 5(2):110-122, 2006.
-
(2006)
IEEE Transactions on Nanotechnology
, vol.5
, Issue.2
, pp. 110-122
-
-
Hogg, T.1
Chen, Y.2
Kuekes, P.3
-
11
-
-
44149111630
-
Prospects for logic-on-a-wire
-
K. E. Moselund et al. Prospects for logic-on-a-wire. Microelectronic Engineering, (85):1406-1409, 2008.
-
(2008)
Microelectronic Engineering
, vol.85
, pp. 1406-1409
-
-
Moselund, K.E.1
-
13
-
-
33846389740
-
Silicon-nanowire transistors with intruded nickel-silicide contacts
-
W. M. Weber et al. Silicon-nanowire transistors with intruded nickel-silicide contacts. Nano Letters, 6(12):2660-2666, 2006.
-
(2006)
Nano Letters
, vol.6
, Issue.12
, pp. 2660-2666
-
-
Weber, W.M.1
-
14
-
-
0141510585
-
Large-scale hierarchical organization of nanowire arrays for integrated nanosystems
-
D. Whang, S. Jin, Y. Wu, and C. M. Lieber. Large-scale hierarchical organization of nanowire arrays for integrated nanosystems. Nano Letters, 3(9):1255-1259, 2003.
-
(2003)
Nano Letters
, vol.3
, Issue.9
, pp. 1255-1259
-
-
Whang, D.1
Jin, S.2
Wu, Y.3
Lieber, C.M.4
-
15
-
-
20144387749
-
One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography
-
W. Wu et al. One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography. Applied Physics A: Materials Science and Processing, 80(6):1173-1178, 2005.
-
(2005)
Applied Physics A: Materials Science and Processing
, vol.80
, Issue.6
, pp. 1173-1178
-
-
Wu, W.1
-
16
-
-
47249095732
-
An integrated phase change memory cell with Ge nanowire diode for cross-point memory
-
June
-
Y. Zhang et al. An integrated phase change memory cell with Ge nanowire diode for cross-point memory. VLSI Technology, 2007 IEEE Symposium on, pages 98-99, June 2007.
-
(2007)
VLSI Technology, 2007 IEEE Symposium on
, pp. 98-99
-
-
Zhang, Y.1
|