Variability-aware design of multilevel logic decoders for nanoscale crossbar memories

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 11, 2008, Pages 2053-2067

  Jamaa, Mohamed Haykel Ben ^a   Moselund, Kirsten Emile ^a   Atienza, David ^a,b   Bouvet, Didier ^a   Ionescu, Adrian Mihai ^a   Leblebici, Yusuf ^a   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Addressing; Crossbar architecture; Memory; Multivalued logic (MVL); Nanotechnology; Reliability

Indexed keywords

CODES (SYMBOLS); DATA STORAGE EQUIPMENT; DIFFERENTIATION (CALCULUS); LITHOGRAPHY; MANY VALUED LOGICS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; THRESHOLD VOLTAGE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

ADDRESSING; ADDRESSING SCHEMES; AREA SAVINGS; CODE SPACES; CRITICAL PARTS; CROSSBAR ARCHITECTURE; CROSSBAR ARRAYS; CRUCIAL PARAMETERS; DECODER CIRCUITS; DECODER DESIGNS; EMERGING TECHNOLOGIES; HIGH VARIABILITIES; LOGIC LEVELS; MEMORY; MEMORY AREAS; MULTILEVEL; MULTIVALUED LOGIC (MVL); MULTIVALUED LOGICS; NANOSCALE CROSSBARS; NW DEVICES; OPTIMAL CODES; OPTIMAL COMBINATIONS; PRECISE; TECHNOLOGICAL SOLUTIONS; TWO TYPES;

DECODING;

EID: 54949085010     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2006076     Document Type: Article

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