Schottky barrier nano-MOSFET with an asymmetrically oxidized source/drain structure

Solid-State Electronics

Volumn 54, Issue 1, 2010, Pages 48-51

  Baghbani Parizi, K ^a   Peyvast, N ^a   Kheyraddini Mousavi, B ^a   Mohajerzadeh, S ^a   Fathipour, M ^a  

^a Thin Film and Nano Electronic Lab   (Iran)

Author keywords

Asymmetric Schottky barrier MOSFET; Barrier height; Fermi level pinning; Thin interfacial oxide; Work function

Indexed keywords

BARRIER HEIGHTS; FERMI LEVEL PINNING; INTERFACIAL OXIDES; SCHOTTKY-BARRIER MOSFET; THIN INTERFACIAL OXIDE;

FERMI LEVEL; FERMIONS; MOSFET DEVICES; WORK FUNCTION;

SCHOTTKY BARRIER DIODES;

EID: 71549157442     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.09.010     Document Type: Article

References (19)

1. Larson J.M., and Snyder J.P. Overview and status of metal S/D Schottky barrier MOSFET technology. IEEE Trans Electron Dev 53 (2006) 1048-1058
2. Xiong S., King T.J., and Bokor J. A comparison study of symmetric ultrathinbody double-gate devices with metal S/D and doped S/D. IEEE Trans Electron Dev 52 8 (2005) 1859-1867
3. Kedzierski J., Xuan P., Anderson E.H., Bokor J., King T.-J., and Hu C.M. Complementary silicide source/drain thin-body MOSFET for the 20 nm gate length regime. IEDM Technol Dig (2000) 57-60
4. Zhu S., Chen J., Li M.-F., Lee S.J., Singh J., Zhu C.X., et al. N-type Schottky barrier source/drain MOSFET using Ytterbium silicide. IEEE Electron Dev Lett 25 8 (2004) 565-567
5. Sun L., Li D.Y., Liu X.Y., and Han R.Q. Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique. Microelectron J 37 4 (2006) 332-335
6. Calvet L.E., Luebben H., Read M.A., Wang C., Synder J.P., and Tucker J.R. Suppression of leakage current in Schottky barrier metal-oxide-semiconductor field-effect-transistor. Appl Phys 91 2 (2002)
7. Jang M., and Lee J. Analysis of Schottky barrier height in small contacts using a thermionic field emission model. ETRI J 24 6 (2004)
8. Monch W. Electronics properties of semiconductor interfaces. Springer 43 (2004)
9. Kobayashi M, Kinoshita A, Saraswat K, Philip Wong HS, Nishi Y. Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET In: Symposium on VLSI technology; 2008. p. 54-5.
10. Magyari-Kope B, Nishi Y, Cho K. Effective work function control by metal-oxide interface characteristics. MRS spring meeting. San Francisco; 2008.
11. Faulkner C., Grupp D.E., and Harris J.S. A new route to zero-barrier metal source/drain MOSFETs Daniel Connelly. IEEE Trans Nanotechnol 3 1 (2004)
12. Tao M., Udeshi D., Basit N., Maldonado E., and Kirk W.P. Removal of dangling bonds and surface states on silicon (0 0 1) with a monolayer of selenium. Appl Phys Lett 82 10 (2003) 1559-1561
13. Zhao T., Breuer U., Rije E., Lenk St., and Mantl S. Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation. Appl Phys Lett 86 6 (2005) 062108-1-062108-3
14. Kinoshita A, Tsuchiya Y, Yagishita A, Uchida K, Koga J. Solution for high performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique. In: VLSI technology; 2004. p. 168-9.
15. Rhoderick E.H., and William R.H. Metal-semiconductor contact. Monographs in electrical and electronic engineering (1988), Clarendon, Oxford (UK)
16. Zhen Zhang. Integration of silicide nanowires as Schottky barrier source/drain in FinFETs. Doctoral thesis, Royal Institute of Technology (KTH) Stockholm, Sweden; 2008.
17. Östling M., and Zaring C. Properties of metal silicides. In: Maex K., and van Rossum M. (Eds) (1995), INSPEC [chapter 2]
18. Yamauchi T., Kinoshita A., Tsuchiya Y., Koga J., and Kato K. One nm NiSi/Si junction design based on first-principle calculation for ultimately low contact resistance. IEDM Tech Dig (2006) 385-388
19. Lu J.P., Miles D., Zhao J., Gurba A., Xu Y., Lin C., et al. A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length. IEDM Tech Dig (2002) 371-374