MPSoC power estimation framework at transaction level modeling

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2007, Pages 245-248

  Atitallah, Rabie Ben ^a   Niar, Smail ^a   Dekeyser, Jean Luc ^a  

^a INRIA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MICROELECTRONICS; MODELS; SPACE RESEARCH;

ANALYTICAL EXPRESSIONS; ARCHITECTURAL SIMULATORS; DESIGN FLOWS; DESIGN SPACE EXPLORATIONS; HYBRID POWER; MULTIPROCESSOR SYSTEM ON CHIPS; PARALLELIZED VERSIONS; PHYSICAL MEASUREMENTS; POWER CONSUMPTION; POWER ESTIMATIONS; POWER MODELING; POWER MODELS; SIMULATION SPEED-UP; TRANSACTION LEVEL MODELING;

ARCHITECTURAL DESIGN;

EID: 51849127410     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2007.4497703     Document Type: Conference Paper

References (13)

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