-
3
-
-
70450264485
-
-
Nvidia GT200 Series: http://www.nvidia.com/object/geforce-gtx-280.html.
-
Nvidia GT200 Series
-
-
-
4
-
-
70450226469
-
-
PolyScalar: http://users.csc.calpoly.edu/~franklin/PolyScalar/Home.htm.
-
PolyScalar
-
-
-
5
-
-
70450283258
-
-
SPEC CPU2000: http://www.spec.org/cpu/.
-
(2000)
-
-
-
6
-
-
70450287153
-
-
icsiboost: http://code.google.com/p/icsiboost/.
-
icsiboost: http://code.google.com/p/icsiboost/.
-
-
-
-
7
-
-
4644245377
-
Adaptive Cache Compression for High-Performance Processors
-
Washington, DC, USA, IEEE Computer Society
-
A. R. Alameldeen and D. A. Wood. Adaptive Cache Compression for High-Performance Processors. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture, pages 212-223, Washington, DC, USA, 2004. IEEE Computer Society.
-
(2004)
ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture
, pp. 212-223
-
-
Alameldeen, A.R.1
Wood, D.A.2
-
8
-
-
36948999941
-
-
University of California, Irvine, School of Information and Computer Sciences
-
A. Asuncion and D. Newman. UCI Machine Learning Repository, University of California, Irvine, School of Information and Computer Sciences, 2007. http://www.ics.uci.edu/~mlearn/MLRepository.html.
-
(2007)
UCI Machine Learning Repository
-
-
Asuncion, A.1
Newman, D.2
-
9
-
-
33747448830
-
Cache Management System Using Virtual and Real Tags in The Cache Directory
-
April
-
S. Bederman. Cache Management System Using Virtual and Real Tags in The Cache Directory. IBM Technical Disclosure, 21(11), April 1979.
-
(1979)
IBM Technical Disclosure
, vol.21
, Issue.11
-
-
Bederman, S.1
-
10
-
-
84957870821
-
VPR: A New Packing, Placement and Routing Tool for FPGA Research
-
London, UK, Springer-Verlag
-
V. Betz and J. Rose. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In FPL '97: Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pages 213-222, London, UK, 1997. Springer-Verlag.
-
(1997)
FPL '97: Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
, pp. 213-222
-
-
Betz, V.1
Rose, J.2
-
11
-
-
47349089048
-
Revisiting the Sequential Programming Model for Multi-Core
-
December
-
M. J. Bridges, N. Vachharajani, Y. Zhang, T. Jablin, and D. I. August. Revisiting the Sequential Programming Model for Multi-Core. In Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 69-84, December 2007.
-
(2007)
Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO)
, pp. 69-84
-
-
Bridges, M.J.1
Vachharajani, N.2
Zhang, Y.3
Jablin, T.4
August, D.I.5
-
13
-
-
33845903561
-
Cooperative Caching for Chip Multiprocessors
-
Washington, DC, USA, IEEE Computer Society
-
J. Chang and G. S. Sohi. Cooperative Caching for Chip Multiprocessors. In ISCA '06: Proceedings of the 33rd Annual International Symposium on Computer Architecture, pages 264-276, Washington, DC, USA, 2006. IEEE Computer Society.
-
(2006)
ISCA '06: Proceedings of the 33rd Annual International Symposium on Computer Architecture
, pp. 264-276
-
-
Chang, J.1
Sohi, G.S.2
-
14
-
-
47349109167
-
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
-
Washington, DC, USA, IEEE Computer Society
-
M. Chu, R. Ravindran, and S. Mahlke. Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. In MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pages 369-380, Washington, DC, USA, 2007. IEEE Computer Society.
-
(2007)
MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 369-380
-
-
Chu, M.1
Ravindran, R.2
Mahlke, S.3
-
15
-
-
70450274276
-
-
Douglas C. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report CS-TR-1997-1342, University of Wisconsin, Madison, June 1997
-
Douglas C. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report CS-TR-1997-1342, University of Wisconsin, Madison, June 1997.
-
-
-
-
16
-
-
54749086399
-
Varieties of Exploratory Experimentation in Nanotoxicology
-
K. C. Elliott. Varieties of Exploratory Experimentation in Nanotoxicology. History and Philosophy of the Life Sciences, 29(3), 2007.
-
(2007)
History and Philosophy of the Life Sciences
, vol.29
, Issue.3
-
-
Elliott, K.C.1
-
17
-
-
85008031236
-
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
-
A. J. KleinOsowski and D. J. Lilja. MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. IEEE Computer Architecture Letters, 1(1):7, 2006.
-
(2006)
IEEE Computer Architecture Letters
, vol.1
, Issue.1
, pp. 7
-
-
KleinOsowski, A.J.1
Lilja, D.J.2
-
19
-
-
33847285070
-
Algorithms for Parallel Boosting
-
Washington, DC, USA, IEEE Computer Society
-
F. Lozano and P. Rangel. Algorithms for Parallel Boosting. In ICMLA '05: Proceedings of the Fourth International Conference on Machine Learning and Applications, pages 368-373, Washington, DC, USA, 2005. IEEE Computer Society.
-
(2005)
ICMLA '05: Proceedings of the Fourth International Conference on Machine Learning and Applications
, pp. 368-373
-
-
Lozano, F.1
Rangel, P.2
-
20
-
-
49749127238
-
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches
-
M. Kleanthous and Y. Sazeides. CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. In Design, Automation and Test in Europe, 2008 (DATE '08), pages 1426-1431.
-
Design, Automation and Test in Europe, 2008 (DATE '08)
, pp. 1426-1431
-
-
Kleanthous, M.1
Sazeides, Y.2
-
21
-
-
0037417074
-
Monte Carlo Algorithms for Stationary Device Simulations
-
M. Nedjalkov, H. Kosina, and S. Selberherr. Monte Carlo Algorithms for Stationary Device Simulations. Mathematics and Computers in Simulation, 62(3-6):453-461, 2003.
-
(2003)
Mathematics and Computers in Simulation
, vol.62
, Issue.3-6
, pp. 453-461
-
-
Nedjalkov, M.1
Kosina, H.2
Selberherr, S.3
-
23
-
-
0033075272
-
Functional Implementation Techniques for CPU Cache Memories
-
J.-K. Peir, W. W. Hsu, and A. J. Smith. Functional Implementation Techniques for CPU Cache Memories. IEEE Transactions on Computers, 48(2):100-110, 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, Issue.2
, pp. 100-110
-
-
Peir, J.-K.1
Hsu, W.W.2
Smith, A.J.3
-
24
-
-
0035691556
-
Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery
-
December
-
J. Ray, J. Hoe, and B. Falsafi. Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery. In Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, (MICRO-34), pages 214-224, December 2001.
-
(2001)
Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, (MICRO-34)
, pp. 214-224
-
-
Ray, J.1
Hoe, J.2
Falsafi, B.3
-
25
-
-
0025448521
-
The Strength of Weak Learnability
-
Robert E. Schapire. The Strength of Weak Learnability. Machine Learning, 5:197-227, 1990.
-
(1990)
Machine Learning
, vol.5
, pp. 197-227
-
-
Schapire, R.E.1
-
26
-
-
0032597692
-
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
-
Washington, DC, USA, IEEE Computer Society
-
E. Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. In FTCS '99: Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, pages 84-91, Washington, DC, USA, 1999. IEEE Computer Society.
-
(1999)
FTCS '99: Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
, pp. 84-91
-
-
Rotenberg, E.1
-
27
-
-
0030149507
-
CACTI: An Enhanced Cache Access and Cycle Time Model
-
May
-
S. Wilton and N. Jouppi. CACTI: An Enhanced Cache Access and Cycle Time Model. IEEE Journal of Solid-State Circuits, 31(5):677-688, May 1996.
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.5
, pp. 677-688
-
-
Wilton, S.1
Jouppi, N.2
-
28
-
-
19244385366
-
High-Volume Data Hiding in Images: Introducing Perceptual Criteria into Quantization Based Embedding
-
May
-
K. Solanki, N. Jacobsen, S. Chandrasekaran, U. Madhow, and B. S. Manjunath. High-Volume Data Hiding in Images: Introducing Perceptual Criteria into Quantization Based Embedding. In Proceedings of the IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), volume 4, pages 3485-3488, May 2002.
-
(2002)
Proceedings of the IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP)
, vol.4
, pp. 3485-3488
-
-
Solanki, K.1
Jacobsen, N.2
Chandrasekaran, S.3
Madhow, U.4
Manjunath, B.S.5
-
29
-
-
85127438349
-
Learning With Ensembles: How Overfitting Can Be Useful
-
D. S. Touretzky, M. C. Mozer, and M. E. Hasselmo, editors, The MIT Press
-
P. Sollich and A. Krogh. Learning With Ensembles: How Overfitting Can Be Useful. In D. S. Touretzky, M. C. Mozer, and M. E. Hasselmo, editors, Advances in Neural Information Processing Systems, volume 8, pages 190-196. The MIT Press, 1996.
-
(1996)
Advances in Neural Information Processing Systems
, vol.8
, pp. 190-196
-
-
Sollich, P.1
Krogh, A.2
-
30
-
-
70450251200
-
-
D. J. Sorin, M. M. K. Martin, M. D. Hill, and D. A. Wood. Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance. (TR-1420), October 2000.
-
D. J. Sorin, M. M. K. Martin, M. D. Hill, and D. A. Wood. Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance. (TR-1420), October 2000.
-
-
-
-
31
-
-
33745198176
-
The STAMPede Approach to Thread-Level Speculation
-
J. G. Steffan, C. Colohan, A. Zhai, and T. C. Mowry. The STAMPede Approach to Thread-Level Speculation. ACM Transactions on Computer Systems, 23(3):253-300, 2005.
-
(2005)
ACM Transactions on Computer Systems
, vol.23
, Issue.3
, pp. 253-300
-
-
Steffan, J.G.1
Colohan, C.2
Zhai, A.3
Mowry, T.C.4
-
32
-
-
84978382687
-
Memory Mesource Management in VMware ESX Server
-
C. A. Waldspurger. Memory Mesource Management in VMware ESX Server. SIGOPS Operating Systems Review, 36(SI):181-194, 2002.
-
(2002)
SIGOPS Operating Systems Review
, vol.36
, Issue.SI
, pp. 181-194
-
-
Waldspurger, C.A.1
-
33
-
-
35348861182
-
DRAMsim: A Memory System Simulator
-
D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMsim: A Memory System Simulator. ACM SIGARCH Computer Architecture News, 33(4):100-107, 2005.
-
(2005)
ACM SIGARCH Computer Architecture News
, vol.33
, Issue.4
, pp. 100-107
-
-
Wang, D.1
Ganesh, B.2
Tuaycharoen, N.3
Baynes, K.4
Jaleel, A.5
Jacob, B.6
|