Functional implementation techniques for CPU cache memories

IEEE Transactions on Computers

Volumn 48, Issue 2, 1999, Pages 100-110

  Peir, Jih Kwon ^a,b   Hsu, Windsor W ^a,c,d   Smith, Alan Jay ^a,c  

^a IEEE   (United States)

^b University of Florida   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IBM ALMADEN RESEARCH CENTER   (United States)

Author keywords

Address translation; Cache access mechanism; Cache area and bandwidth; Cache memory

Indexed keywords

BANDWIDTH; CONSTRAINT THEORY; DATA ACQUISITION; RESPONSE TIME (COMPUTER SYSTEMS);

ADDRESS TRANSLATION; CACHE ACCESS MECHANISMS;

BUFFER STORAGE;

EID: 0033075272     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.752651     Document Type: Article

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