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Volumn , Issue , 2005, Pages

ESD protection for advanced CMOS SOI technologies

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED CMOS; BULK DEVICES; CIRCUIT LEVELS; DESIGN METHODOLOGY; DEVICE SIZES; ESD PROTECTION; ESD STRESS; RESPONSE SURFACE METHOD; SOI-MOSFETS; SPICE SIMULATIONS; TEST CIRCUIT; TEST DATA; TEST RESULTS;

EID: 70449724917     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (25)
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  • 6
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    • available at
    • Verilog-A Reference Manual, available at http://eesof.tm.agilent.com/ docs/adsdoc2004A/v erilogaref/index.html
    • Reference Manual
    • Verilog-A1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.