ESD protection for SOI technology using an under-the-box (substrate) diode structure

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2004, Pages

  Salman, Akram ^a   Pelella, Mario ^a   Beebe, Stephen ^a   Subba, Niraj ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED OXIDES; DEEP N-WELL; DIODE STRUCTURE; ESD PROTECTION; PROCESS SIMULATIONS; PROTECTION LEVEL; SELF-HEATING EFFECT; SOI DIODE; SOI SUBSTRATES; SOI TECHNOLOGY; SOI WAFERS; STANDARD CMOS PROCESS;

CMOS INTEGRATED CIRCUITS; DIODES; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; SILICON ON INSULATOR TECHNOLOGY; STANDARDS;

SILICON WAFERS;

EID: 77950788507     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2004.5272603     Document Type: Conference Paper

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