Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 81-94

  Torres, Cynthia A ^a   Miller, James W ^a   Stockinger, Michael ^a   Akers, Matthew D ^a   Khazhinsky, Michael G ^a   Weldon, James C ^a  

^a MOTOROLA INC   (United States)

Author keywords

Bipolar transistors; Clamps; CMOS technology; Electrostatic discharge; MOSFET circuits; Optimization methods; Protection; Rails; Semiconductor device modeling; SPICE

Indexed keywords

BIPOLAR TRANSISTORS; CIRCUIT SIMULATION; CLAMPING DEVICES; CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; RAILS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SPICE; TRANSISTORS;

ADVANCED CMOS; CMOS TECHNOLOGY; COMPACT MODEL; ESD PROTECTION; MOSFET CIRCUITS; OPTIMIZATION METHOD; PROTECTION; SPICE SIMULATIONS;

MOSFET DEVICES;

EID: 84948960517     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. T. Polgreen and A. Chatterjee, "Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow," EOS/ESD Symposium Proceedings, 1989
2. A. Amerasekera and J. Seitchik, "Electrothermal Behavior of Deep Submicron NMOS Transistors Under High Current Snapback (ESD/EOS) Conditions," IEDM Tech. Digest, p.455, 1994
3. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley &Sons, 1995
4. X. Guggenmos, "ESD Related Device and Circuit Modeling at Siemens," ESPRIT ESDEM Public Workshop on ESD Protection Design Methodology Proceedings, Zurich, February 1999
5. E. Worley, A. Salem, and Y. Sittampalam, "High Current Characteristics of Devices in a 0.18m CMOS Technology," EOS/ESD Symposium Proceedings, 2000
6. R. Merril and E. Issaq, "ESD Design Methodology," EOS/ESD Symposium Proceedings, 1993
7. S. Dabral, R. Aslett, and T. Maloney, "Core Clamps for Low Voltage Technologies," EOS/ESD Symposium Proceedings, 1994
8. T. Maloney and S. Dabral, "Novel Clamp Circuits for IC Power Supply Protection," EOS/ESD Symposium Proceedings, 1995
9. E. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, "Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions," EOS/ESD Symposium Proceedings, 1995
10. W. Anderson, J. Montanaro, and N. Howorth, "Cross-Referenced ESD Protection for Power Supplies," EOS/ESD Symposium Proceedings, 1998
11. J. Miller, C. Torres, and T. Cooper, U.S. Patent 5,946,177 (1999)
12. J. Miller, M. Khazhinsky, J. Weldon, "Engineering the Cascoded NMOS Output Buffer for Maximum Vt1," EOS/ESD Symposium Proceedings, 2000
13. S. Ghandi, Semiconductor Power Devices, John Wiley &Sons, 1977, Chapter 4, p. 140
14. S. Voldman, V. Gross, M. Hargrove, J. Never, J. Slinkman, M. O'Boyle, T. Scott, and J. Delecki, Shallow Trench Isolation Double-Diode Electrostatic Discharge Circuit And Interaction With DRAM Output Circuitry, EOS/ESD Symposium Proceedings, 1992
15. S. Dabral, R. Aslett, and T. Maloney, Designing On-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity, EOS/ESD Symposium Proceedings, 1993
16. S. Voldman, "ESD Protection in a Mixed Voltage Interface and Multi-rail Disconnected Power Grid Environment in 0.50 and 0.25m CMOS Technologies," EOS/ESD Symposium Proceedings, 1994
17. S. Voldman, G. Gerosa, V. Gross, N. Dickson, S. Furkay, and J. Slinkman, Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors, EOS/ESD Symposium Proceedings, 1995
18. S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley &Sons, 1998
19. F. Takeda and J. Miller, Patent application filed with USPTO, April 2000
20. H. Stubing and H.-M. Rein, A compact physical large-signal model for high-speed bipolar transistors at high current densities-Part I: One dimensional model, IEEE Trans. Electron Devices, vol. 34, pp.1741-1751, 1987
21. H.-M. Rein and M. Schroter, A compact physical large-signal model for high-speed bipolar transistors at high current densities-Part II: Two dimensional model and experimental results, IEEE Trans. Electron Devices, vol. 34, pp.1752-1761, 1987
22. A. Koldehoff, M. Schroter, and H.-M. Rein, A compact bipolar transistor model for very highfrequency-applications with special regard to narrow emitter stripes and high current densities, Solid-State Electron., vol. 36, pp. 1035-1048, 1993
23. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd ed., McGraw-Hill, Inc. 1993
24. C. Diaz, S. Kang, C. Duvvury, Modeling of Electrical Overstress in Integrated Circuits, Kluwer Academic Publishers, pp. 6-7, 1995
25. H. Tireford, "MICO, a Multi-platform Tool for Circuit Optimization," Motorola Internal Report