Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2004, Pages

  Khazhinsky, Michael G ^a   Miller, James W ^a   Stockinger, Michael ^a   Weldon, James C ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED CMOS; BIAS CIRCUITS; CIRCUIT DESIGNS; EXPERIMENTAL DATA; FRAGILE DEVICES; OUTPUT BUFFER; SERIES RESISTOR;

CIRCUIT SIMULATION; MOS DEVICES; SAFETY ENGINEERING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 77950807063     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2004.5272600     Document Type: Conference Paper

References (18)

1. A. Amerasekera and J. Seitchik, "Electrothermal Behavior of Deep Submicron nMOS Transistors Under High Current Snapback (ESD/EOS) Conditions," IEDM Tech. Digest, 1994, pp.455-8.
2. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley & Sons, 1995.
3. T. Polgreen and A. Chatterjee, "Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow," EOS/ESD Symp. Proc., 1989, pp.167-74.
4. D. Krakauer, and K. Mistry, "ESD Protection in a 3.3V Sub-micron Silicided CMOS Technology," EOS/ESD Symp. Proc., 1992, pp.250-7.
5. S. Voldman, "ESD Protection in a Mixed Voltage Interface and Multi-rail Disconnected Power Grid Environment in 0.50 and 0.25μm CMOS Technologies," EOS/ESD Symp. Proc., 1994, pp.125-34.
6. S. Voldman, J. Never, S. Holmes, and J. Adkisson, "Linewidth Control Effects on MOSFET ESD Robustness," EOS/ESD Symp. Proc., 1996, pp.101-9.
7. W. Anderson, and D. Krakauer, "ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration," EOS/ESD Symp. Proc., 1998, pp.54-62.
8. J. W. Miller, M. G. Khazhinsky, J. C. Weldon, "Engineering the Cascoded NMOS Output Buffer for Maximum Vt1," EOS/ESD Symp. Proc., 2000, pp.308-17.
9. J. Smith, "An Anti-Snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction During ESD Events," EOS/ESD Symp. Proc., 1999, pp.62-9. (Pubitemid 32262405)
10. G.C-F Yeap et al., "A 100 nm Copper/Low-K Bulk CMOS Technology with Multi Vt and Multi Gate Oxide Integrated Transistors for Low Standby Power, High Performance and RF/Analog System on Chip Applications," VLSI Technology Symposium Proc., 2002, pp.16-7.
11. C. Duvvury and C. Diaz, "Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection," Proc. 30th Int. Reliability Physics Symp., 1992, pp.141-50. (Pubitemid 23574222)
12. M. Stockinger, J. W. Miller, M. G. Khazhinsky, C. A. Torres, J. C. Weldon, B. D. Preble, M. J. Bayer, M. Akers, and V. G. Kamat, "Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies," EOS/ESD Symp. Proc., 2003, pp.17-26.
13. DIOS-ISE, DESSIS-ISE Manuals. Release 9.5 ISE. 2004.
14. S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, 1981
15. C. Torres, J. W. Miller, M. Stockinger, M. Akers, M. Khazhinsky, and J. Weldon, "Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS," EOS/ESD Symp. Proc., 2001, pp.82-95.
16. R. Merrill and E. Issaq, "ESD Design Methodology," EOS/ESD Symp. Proc., 1993, pp.233-7.
17. E. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen and M. Tennyson, "Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions," EOS/ESD Symp. Proc., 1995, pp.13-20.
18. S. Dabral, R. Aslett, and T.Maloney, "Core Clamps for Low Voltage Technologies," EOS/ESD Symp. Proc., 1993, pp.239-49.