ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages

  Juliano, Patrick A ^a   Anderson, Warren R ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC POWER SYSTEMS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; MICROPROCESSOR CHIPS;

CAD TOOL; CHIP ASSEMBLY; CMOS SOI TECHNOLOGY; ESD PROTECTION; PIN COUNTS; POWER SUPPLY;

INTEGRATED CIRCUIT DESIGN;

EID: 84945208767     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. I. W. Miller, M.G. Khazhinsky, and IC. Weldon, "Engineering the cascoded NMOS Output Buffer for Maximum VII, " Proc. EOSIESD Symp., pp. 308-317, 2000.
3. S. Voldman, "ESD Protection in SOl CMOS Technology with Al and Cu Interconnects in Advanced Microprocessor Semiconductor Chips, " Proc. EOSIESD Symp., pp. 105-115, 1999.
4. J. Kowaleski, Jr. et al., "Implementation of an Alpha Microprocessor in SOl, " Proc. Int. Solid-State Circuits Conj, pp.248-249, 2003.
5. T. Maloney and W. Kan, "Stacked PMOS Clamps for Hgh Voltage Power Supply Protection, " Proc. EOSIESD Symp., pp. 70-77, 1999.
6. W. Anderson et al., "Cross-Referenced ESD Protection for Power Supplies, " Proc. EOSIESD Symp., pp. 86-95, 1998.
7. C. Torres et al., "Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies, " Proc. EOSIESD Symp., pp. 82-95, 2001.
8. S. Sinha et aI., "An automated Tool for Detecting ESD Design Errors, " Proc. EOSIESD Symp., pp. 208-217, 1998.