Asymmetric dual-gate multi-Fin keeper bias options and optimization for low power and robust FinFET domino logic

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 1720-1723

  Tawfik, Sherif A ^a   Kursun, Volkan ^b  

^a Wisconsin Electric Machines and Power Electronics Consortium   (United States)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OPERATIONS; CIRCUIT TECHNIQUES; DOMINO CIRCUITS; DOMINO LOGIC; DOMINO LOGIC CIRCUITS; DOUBLE GATES; GATE BIAS; KEEPER TRANSISTORS; LOW-POWER; NOISE IMMUNITIES; NOISE MARGINS; POWER CONSUMPTION; POWER REDUCTIONS; SPEED ENHANCEMENTS; VARIABLE THRESHOLDS;

DELAY CIRCUITS; ELECTRIC POWER UTILIZATION; FIELD EFFECT TRANSISTORS; SWITCHING CIRCUITS; THRESHOLD VOLTAGE;

LOGIC CIRCUITS;

EID: 62949094689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746371     Document Type: Conference Paper

References (7)

1. S. A. Tawfik and V. Kursun, "Low-Power and Compact Sequential Circuits with Independent-Gate FinFETs," IEEE Transactions on Electron Devices, Vol. 55, Number 1, pp. 60-70, January 2008.
2. V. Kursun and E. G. Friedman, "Domino Logic With Variable Threshold Voltage Keeper," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, pp. 1080-1093, December 2003.
3. A. Alvandpour et al., "A Sub-130-nm Conditional Keeper Technique," IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, pp. 633-638, May 2002.
4. Medici Device Simulator, Synopsys, Inc., 2006.
5. M. W. Allam, M. H. Anis, and M. I. Elmasry, "High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies," Proceedings of the IEEE International Symposium on Low-Power Electronics Design, pp. 155-160, July 2000.
6. Z. Liu and V. Kursun, "Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages," Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 31-36, March 2006.
7. S. A. Tawfik and V. Kursun, "High Speed FinFET Domino Logic Circuits with Independent Gate-Biased Double-Gate Keepers Providing Dynamically Adjusted Immunity to Noise," Proceedings of the IEEE International Conference on Microelectronics, pp. 186-189, December 2007.