Channel-stress enhancement characteristics for scaled pMOSFETs by using damascene gate with top-cut compressive stress liner and eSiGe

IEEE Transactions on Electron Devices

Volumn 56, Issue 11, 2009, Pages 2778-2784

  Mayuzumi, Satoru ^a,b   Yamakawa, Shinya ^a   Kosemura, Daisuke ^b   Takei, Munehisa ^b   Tateshita, Yasushi ^a   Wakabayashi, Hitoshi ^a   Tsukamoto, Masanori ^a   Ohno, Terukazu ^a   Ogura, Atsushi ^b   Nagashima, Naoki ^a  

^a SONY CORPORATION   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

Channel stress; Damascene gate; ESiGe; Gate last; High k; Hole mobility; Metal gate; Stress simulation; Top cut stress liner; UV Raman spectroscopy

Indexed keywords

CHANNEL STRESS; DAMASCENE GATE; ESIGE; GATE LAST; HIGH-K; METAL GATE; STRESS SIMULATION; UV-RAMAN SPECTROSCOPY;

COMPRESSIVE STRESS; RAMAN SCATTERING; RAMAN SPECTROSCOPY; SILICON NITRIDE; SOLID-STATE SENSORS; TENSILE STRESS;

HOLE MOBILITY;

EID: 70350724627     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2031002     Document Type: Article

References (14)

1. S. Mayuzumi, S. Yamakawa, Y. Tateshita, T. Hirano, M. Nakata, S. Yamaguchi, K. Tai, H. Wakabayashi, M. Tsukamoto, and N. Nagashima, "High-performance metal/high- k n- and p-MOSFETs with top-cut dual stress liners using gate-last damascene process on (100) substrates," IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 620-626, Apr. 2009.
2. 2 SRAM cell size in a 291 Mb array," in IEDM Tech. Dig., Dec. 2008, pp. 941-943.
3. 2 gate stack by low temperature process," in IEDM Tech. Dig., Dec. 2005, pp. 890-893.
4. Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kitamura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimito, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima, "High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates," in IEDM Tech. Dig., Dec. 2006, pp. 63-66.
5. 2 gate stack using novel Si extrusion process for high performance application," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 208-209.
6. 2 gate stack on (110) substrate by low temperature process," in Proc. ESSDERC, Sep. 2006, pp. 121-124.
7. S. Yamaguchi, K. Tai, T. Hirano, T. Ando, S. Hiyama, J. Wang, Y. Hagimoto, Y. Nagahama, T. Kato, K. Nagano, M. Yamanaka, S. Terauchi, S. Kanda, R. Yamamoto, Y. Tateshita, Y. Tagawa, H. Iwamoto, M. Saito, N. Nagashima, and S. Kadomura, "High performance dual metal gate CMOS with high mobility and low threshold voltage applicable to bulk CMOS technology," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 152-153.
8. J. Wang, Y. Tateshita, S. Yamakawa, K. Nagano, T. Hirano, Y. Kikuchi, Y. Miyanami, S. Yamaguchi, K. Tai, R. Yamamoto, S. Kanda, T. Kimura, K. Kugimiya, M. Tsukamoto, H. Wakabayashi, Y. Tagawa, H. Iwamoto, T. Ohno, M. Saito, S. Kadomura, and N. Nagashima, "Novel channel-stress enhancement technology with eSiGe S/D and recessed channel on damascene gate process," in VLSI Symp. Tech. Dig., Jun. 2007, pp. 46-47.
9. S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, "A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films," in IEDM Tech. Dig., Dec. 2004, pp. 213-216.
10. A. Ogura, K. Yamasaki, D. Kosemura, S. Tanaka, I. Chiba, and R. Shimizu, "UV-Raman spectroscopy system for local and global strain measurements in Si," Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3007-3011, Apr. 2006.
11. D. Kosemura, Y. Kakemura, T. Yoshida, A. Ogura, M. Kohno, T. Nishita, and T. Nakanishi, "Characterization of strain for high-performance metal-oxide-semiconductor field-effect-transistor," Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2538-2543, Apr. 2008.
12. S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, "Uniaxial-process-induced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
13. I. De Wolf, "Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits," Semicond. Sci. Technol., vol. 11, no. 2, pp. 139-154, Feb. 1996.
14. S. Yamakawa, S. Mayuzumi, J. Wang, Y. Tateshita, H. Wakabayashi, T. Ohno, H. Ansai, D. Kosemura, M. Takei, and A. Ogura, "Study of stress effect on replacement gate technology with compressive stress liner and eSiGe for pFETs," in Proc. SISPAD, Sep. 2008, pp. 109-112.