Novel channel-stress enhancement technology with eSiGe S/D and recessed channel on damascene gate process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 46-47

  Wang, J ^a   Tateshita, Y ^a   Yamakawa, S ^a   Nagano, K ^a   Hirano, T ^a   Kikuchi, Y ^a   Miyanami, Y ^a   Yamaguchi, S ^a   Tai, K ^a   Yamamoto, R ^a   Kanda, S ^a   Kimura, T ^a   Kugimiya, K ^a   Tsukamoto, M ^a   Wakabayashi, H ^a   Tagawa, Y ^a   Iwamoto, H ^a   Ohno, T ^a   Saito, M ^a   Kadomura, S ^a   Nagashima, N ^a   more..

^a SONY CORPORATION   (Japan)

Author keywords

Channel; Damascene gate; Embedded SiGe; High k metal gate; Mobility enhancement; Recessed channel; Stress

Indexed keywords

MOSFET DEVICES;

CHANNEL STRAIN; DAMASCENE GATE PROCESS; DAMASCENE PROCESSING; GATE STACKS; LOW POWERS; RECESSED CHANNEL (RCH); STRESS ENHANCEMENT; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 47249084668     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339721     Document Type: Conference Paper

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