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Volumn , Issue , 2008, Pages 109-112

Study of stress effect on replacement gate technology with compressive stress liner and eSiGe for pFETs

Author keywords

Damascene gate; Gate last; Mobility enhancement; Raman spectroscopy; Replacement gate; Simulation; Strain; Stress

Indexed keywords

DAMASCENE-GATE; GATE-LAST; MOBILITY ENHANCEMENT; REPLACEMENT-GATE; SIMULATION;

EID: 67650391326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2008.4648249     Document Type: Conference Paper
Times cited : (12)

References (10)
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    • Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates
    • S. Mayuzumi et al., "Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates", IEDM Tech. Dig., pp.293-296 (2007)
    • (2007) IEDM Tech. Dig , pp. 293-296
    • Mayuzumi, S.1
  • 2
    • 50249185641 scopus 로고    scopus 로고
    • A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
    • K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Tech. Dig., pp.247-250 (2007)
    • (2007) IEDM Tech. Dig , pp. 247-250
    • Mistry, K.1
  • 3
    • 84901362411 scopus 로고    scopus 로고
    • Analysis of Novel Stress Enhancement Effect Based on Damascene Gate Process with eSiGe S/D for pFETs
    • S. Yamakawa et al., "Analysis of Novel Stress Enhancement Effect Based on Damascene Gate Process with eSiGe S/D for pFETs", Proc. SISPAD 2007, pp.109-112 (2007)
    • (2007) Proc. SISPAD 2007 , pp. 109-112
    • Yamakawa, S.1
  • 4
    • 47249084668 scopus 로고    scopus 로고
    • Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
    • J. Wang et al., "Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process", Symp. VLSI Tech., pp.46-47 (2007)
    • (2007) Symp. VLSI Tech , pp. 46-47
    • Wang, J.1
  • 5
    • 33646916313 scopus 로고    scopus 로고
    • UV-Raman Spectroscopy System for Local and Global Strain Measurements in Si
    • A. Ogura et al., "UV-Raman Spectroscopy System for Local and Global Strain Measurements in Si", Jpn. J. Appl. Phys. vol.45, pp.3007-3011 (2006)
    • (2006) Jpn. J. Appl. Phys , vol.45 , pp. 3007-3011
    • Ogura, A.1
  • 6
    • 63149133130 scopus 로고    scopus 로고
    • Characterization of Strain in Si for High Performance MOSFETs
    • D. Kosemura et al., "Characterization of Strain in Si for High Performance MOSFETs", Proc. SSDM 2007, pp.390-391 (2007)
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    • Kosemura, D.1
  • 7
    • 51949110479 scopus 로고    scopus 로고
    • Channel-Stress Study on Gate-Size Effects for Damascene-Gate pMOSFETs with Top-Cut Compressive Stress Liner and eSiGe
    • S. Mayuzumi et al., "Channel-Stress Study on Gate-Size Effects for Damascene-Gate pMOSFETs with Top-Cut Compressive Stress Liner and eSiGe", Symp. VLSI Tech., pp.126-127 (2008)
    • (2008) Symp. VLSI Tech , pp. 126-127
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  • 8
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  • 9
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    • Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits
    • I.D. Wolf, "Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits", Semicond. Sci. Technol. vol.11, pp.139-154 (1996)
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  • 10
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    • Future of Strained Si/Semiconductors in Nanoscale MOSFETs
    • S.E. Thompson et al., "Future of Strained Si/Semiconductors in Nanoscale MOSFETs", IEDM Tech Dig., pp.681-684 (2006)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.