An RT-level fault model with high gate level correlation

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 3-8

  Corno, F ^a   Cumani, G ^a   Sonza Reorda, M ^a   Squillero, G ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Analytical models; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Fault diagnosis; Observability; Redundancy; Test pattern generators

Indexed keywords

ANALYTICAL MODELS; AUTOMATIC TESTING; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; FAULT DETECTION; OBSERVABILITY; REDUNDANCY; RELIABILITY ANALYSIS;

CIRCUIT FAULTS; CIRCUIT TESTING; COMPUTATIONAL MODEL; GOOD CORRELATIONS; SYNTHESIS OPTIMIZATION; TEST PATTERN GENERATIONS; TEST PATTERN GENERATOR; TESTABILITY ANALYSIS;

CIRCUIT SIMULATION;

EID: 84949658137     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889551     Document Type: Conference Paper

References (10)

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