MOSIZ: A two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Dai, Zhi Jian ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX GATES; CONVENTIONAL METHODS; CPU TIME; LOGICAL PATHS; MOS CIRCUITS; MULTI-STAGE; OPTIMAL TIMING; RESPONSE CHARACTERISTIC; TRANSISTOR SIZING;

DELAY CIRCUITS; INTEGRATED CIRCUITS; OPTIMIZATION;

TIMING CIRCUITS;

EID: 26144438998     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56775     Document Type: Conference Paper

References (11)

1. W.T. Nye, et al., "DELIGHT.SPICE: An optimization-based system for the design of integrated circuits", IEEE Proc. Custom Integrated Circuits Conf., pp.233-238, May 1983
2. CM. Lee and H. Soukup, "An algorithm for CMOS timing and area optimization", IEEE J. Solid-State Circuits, vol. SC-19, no. 5, pp. 781-787, Oct. 1984
3. M.D. Matson, "Macromodeling and Optimization of Digital MOS VLSI Circuits", Ph.D. dissertation, Dept of EE & CS, MIT, 1985
4. J.P.Fishburn and A.E.Dunlop."TILOS: A posynomial programming approach to transistor sizing," Proc. Int. Conf. Computer Aided Design, pp.326-328, November 1985
5. J.M.Shyu, et al., "Optimization-Based Transistor Sizing," IEEE Proc. Custom Integrated Circuits Conf., pp.417-420, May 1987
6. M. A. Cirit,"TRANSISTOR SIZING IN CMOS CIRCUITS", 24th ACM/IEEE Design Automation Conference, 1987, pp.121-124
7. K.Asada and J.Mavor,"A MOS Leaf-cell Generation System from Boolean Expressions", IEEE Proc. Custom Integrated Circuits Conf., pp.21-24, May 1987
8. J.Rubinstein, et al., "Signal Delay in RC Tree Network," IEEE Trans, on Computer Aided Design, Vol.CAD-2, No.3, pp.202-211, July 1983
9. E. Polak, "COMPUTATIONAL METHODS IN OPTIMIZATION", Academic Press, 1971
10. K.Asada and Mavor, "Area optimized MOS circuit generation using the circuit synthesis program MOSYN-2", Proc. of 12th European Solid-State Circuit Conf., Delft, The Netherlands, pp.71-73, September 1986
11. Y.Sone, S.Suzuki and K.Asada, "A Gate Matrix Deformation and 3-Dimensional maze routing for dense MOS module generation.", (To be presented CICC'89, May 1989)