Transistor level budgeting for power optimization

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 116-121

  Kursun, E ^a   Ghiasi, S ^a   Sarrafzadeh, M ^a  

^a Engineering IV   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; SYSTEMS ANALYSIS; THEOREM PROVING; TRANSISTORS;

CRITICAL PATH INFORMATION; POWER CIRCUIT DESIGN; POWER OPTIMIZATION; SERIES-PARALLEL (SP) GRAPH;

ELECTRIC POWER UTILIZATION;

EID: 2942640151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283660     Document Type: Conference Paper

References (14)

1. J. P. Fishburn and A. E. Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing", Proceedings of the 1985 International Conference on Computer-Aided Design, pp. 326-328, November 1985.
2. V. Sundararajan, S.S. Sapatnekar, K.K. Parhi, "MINFLOTRANSIT: Min-Cost Flow Based Transistor Sizing Tool", Design Automation Conference, 2000
3. S. Sapatnekar, V. Rao, P. Vaidya, S. Kang, "An exact solution to the Transistor Sizing Problem for CMOS Circuits using convex optimization", IEEE Transactions on Computer Aided Design, vol. 12, pp. 1621-1634, 1993.
4. C. Chen, C.N. Chu, D. F. Wong, "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation", Proceedings of 1998 IEEE/ACM International Conference on Computer Aided Design, pp. 617-624, 1998.
5. H.Y. Chen, S. M. Kang, "A Circuit Optimization Aid for CMOS High Performance Circuits", Integration VLSI Journal, Vol. 10, pp. 185-212, 1991.
6. Z. Dai and K. Asada, "MOSIZ: A two-step Transistor Sizing Algorithm Based on Optimal Timing Assignment Method for Multistage complex Gates", Proceedings of the 1989 Custom Integrated Circuits Conference", pp. 17.3.1-17.3.4, 1989.
7. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis", Technical Report No. UCB/ERL M92/41, University of California Berkeley, 1992.
8. R. Nair, C.L. Berman, P.S. Hauge, E.J. Yoffa, "Generation of Performance Constraints for Layout", Proceedings of IEEE Transactions on Computer Aided Design, Vol.8, No.8, pp 860-874, August 1989.
9. Y. Liao, C.K. Wong, "An Algorithm to Compact VLSI Symbolic Layout with Mixed Constraints", Proceedings of IEEE Transactions on Computer Aided Design, Vol.2, No.2, April, 1983.
10. J.F. Lee, D.T. Trang, "VLSI Layout Compaction with Grid and Mixed Constraints", Proceedings of IEEE Transactions on Computer Aided Design, Vol.6, No.5, Sep, 1987.
11. E. Felt, E. Charbon, E. Malavasi, A. Sarigiovanni-Vincentelli, "An Efficient Methodology for Symbolic Compaction of Analog ICs with Multiple Symmetry Constraints", Proceedings of Conference on European Design Automation, Nov., 1992.
12. T. Vao, P.M. Vaidya, C.L. Liu, "A New Performance Driven Placement Algorithm", Proceedings of International Conference on Computer Aided Design, pp.4447, 1991.
13. H. Youssef, E. Shragowitz, "Timing Constraints for Correct Performance", Proceedings of International Conference on Computer Aided Design, pp.2427, 1990
14. A.R. Conn, I.M. Elfadel, W.W. Molzen, P.R. O'Brien, P.N.Strenski, C. Visweswariah, C.B. Whan, "Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation" Design Automation Conference 1999.