Statistical timing yield optimization by gate sizing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 10, 2006, Pages 1140-1146

  Sinha, Debjit ^a,b   Shenoy, Narendra V ^a,c   Zhou, Hai ^a,b  

^a IEEE   (United States)

^b Northwestern University   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

Gate sizing; Optimization; Statistical gate delay modeling; Statistical timing analysis; Timing yield; Variability; VLSI

Indexed keywords

GATE SIZING; STATISTICAL GATE DELAY MODELING; STATISTICAL TIMING ANALYSIS; TIMING YIELD; VARIABILITY;

GAIN MEASUREMENT; LOGIC CIRCUITS; OPTIMIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

GATES (TRANSISTOR);

EID: 33750594762     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.884166     Document Type: Article

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